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mb/asrock: Add Z77 Extreme4

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New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".

Internal flashing of the entire chip is possible from vendor firmware
by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is
connected to one of the unused pins of the PCIE1 slot.

Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.17.0 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)

Untested:
- Intel VBIOS
- Front USB headers
- Other fans
- LED headers
- eSATA, Toslink
- PCIE1 (x1) slot

Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Riku Viitanen 2024-12-25 23:38:42 +02:00 • committed by Matt DeVillier
commit d97644dd3f
17 changed files with 640 additions and 0 deletions
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32
src/mainboard/asrock/z77_extreme4/Kconfig Normal file
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# SPDX-License-Identifier: GPL-2.0-only
if BOARD_ASROCK_Z77_EXTREME4
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select DRIVERS_ASMEDIA_ASM1061
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_NUVOTON_COMMON_COM_A
select SUPERIO_NUVOTON_NCT6776
select USE_NATIVE_RAMINIT
config CBFS_SIZE
default 0x600000
config MAINBOARD_DIR
default "asrock/z77_extreme4"
config MAINBOARD_PART_NUMBER
default "Z77 Extreme4"
endif

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src/mainboard/asrock/z77_extreme4/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_ASROCK_Z77_EXTREME4
bool "Z77 Extreme4"

8
src/mainboard/asrock/z77_extreme4/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

3
src/mainboard/asrock/z77_extreme4/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

10
src/mainboard/asrock/z77_extreme4/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK,1)
{
Return(Package(){0,0})
}
Method(_PTS,1)
{
}

11
src/mainboard/asrock/z77_extreme4/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#undef SUPERIO_DEV
#undef SUPERIO_PNP_BASE
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define NCT6776_SHOW_SP1 1
#define NCT6776_SHOW_KBC 1
#include "superio/nuvoton/nct6776/acpi/superio.asl"

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src/mainboard/asrock/z77_extreme4/board_info.txt Normal file
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Category: desktop
Board URL: https://www.asrock.com/mb/Intel/Z77%20Extreme4/
ROM protocol: SPI
Flashrom support: y
ROM package: DIP-8
ROM socketed: y
Release year: 2012

8
src/mainboard/asrock/z77_extreme4/cmos.default Normal file
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## SPDX-License-Identifier: GPL-2.0-only
boot_option=Fallback
debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
sata_mode=AHCI
gfx_uma_size=64M

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src/mainboard/asrock/z77_extreme4/cmos.layout Normal file
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## SPDX-License-Identifier: GPL-2.0-only
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 2 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 3 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 4 power_on_after_fail
411 2 e 5 sata_mode
# coreboot config options: northbridge
416 5 e 6 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
# Generic on/off enum
1 0 Disable
1 1 Enable
# boot_option
2 0 Fallback
2 1 Normal
# debug_level
3 0 Emergency
3 1 Alert
3 2 Critical
3 3 Error
3 4 Warning
3 5 Notice
3 6 Info
3 7 Debug
3 8 Spew
# power_on_after_fail
4 0 Disable
4 1 Enable
4 2 Keep
# sata_mode
5 0 AHCI
5 1 Compatible
5 2 Legacy
# gfx_uma_size (Intel IGP Video RAM size)
6 0 32M
6 1 64M
6 2 96M
6 3 128M
6 4 160M
6 5 192M
6 6 224M
6 7 256M
6 8 288M
6 9 320M
6 10 352M
6 11 384M
6 12 416M
6 13 448M
6 14 480M
6 15 512M
6 16 1024M
# -----------------------------------------------------------------
checksums
checksum 392 423 984

BIN
src/mainboard/asrock/z77_extreme4/data.vbt Normal file
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Binary file not shown.

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src/mainboard/asrock/z77_extreme4/devicetree.cb Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
device domain 0 on
device ref host_bridge on
subsystemid 0x1849 0x0150
end
device ref peg10 on
subsystemid 0x1849 0x0151
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
"PCIE2" "SlotDataBusWidth16X"
end
device ref peg11 on
subsystemid 0x1849 0x0155
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
"PCIE3" "SlotDataBusWidth8X"
end
device ref igd on
subsystemid 0x1849 0x0162
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "pcie_port_coalesce" = "1"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "usb_port_config" = "{
{1, 6, 0},
{1, 6, 0},
{1, 1, 1},
{1, 1, 1},
{1, 1, 2},
{1, 1, 2},
{1, 6, 3},
{1, 6, 3},
{1, 6, 4},
{1, 6, 4},
{1, 6, 6},
{1, 1, 5},
{1, 1, 5},
{1, 6, 6},
}"
device ref xhci on
subsystemid 0x1849 0x1e31
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
end
device ref mei1 on
subsystemid 0x1849 0x1e3a
end
device ref ehci2 on
subsystemid 0x1849 0x1e2d
end
device ref hda on
subsystemid 0x1849 0x1898
end
device ref pcie_rp1 on # PCIe x1 slot, "PCIE4"
subsystemid 0x1849 0x1e10
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort"
"PCIE4" "SlotDataBusWidth1X"
end
device ref pcie_rp4 on # ASM1061 SATA Controller
subsystemid 0x1849 0x1e16
device pci 00.0 on end
end
device ref pcie_rp5 on # BCM57781 GbE NIC
subsystemid 0x1849 0x1e18
device pci 00.0 on end
end
device ref pcie_rp6 on # ASM1083 PCI bridge
subsystemid 0x1849 0x1e1a
device pci 00.0 on end
end
device ref pcie_rp7 on # PCIe x1 slot, "PCIE1"
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort"
"PCIE1" "SlotDataBusWidth16X"
end
device ref pcie_rp8 on # ASM1042 USB 3.0 Controller
subsystemid 0x1849 0x1e1e
device pci 00.0 on end
end
device ref ehci1 on
subsystemid 0x1849 0x1e26
end
device ref lpc on
subsystemid 0x1849 0x1e44
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0241"
register "gen3_dec" = "0x000c0251"
chip superio/nuvoton/nct6776
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off end # Parallel port
device pnp 2e.2 on # COM1
# global
irq 0x13 = 0xff
irq 0x14 = 0xff
irq 0x1a = 0xf8
irq 0x1b = 0x0e
irq 0x24 = 0x5c
irq 0x27 = 0xd8
irq 0x2a = 0x62
irq 0x2c = 0x80
# COM1
io 0x60 = 0x3f8
end
device pnp 2e.3 on # COM2, IR
io 0x60 = 0x2f8
irq 0xf1 = 0x5c
end
device pnp 2e.5 on
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 0x01
irq 0x72 = 0x0c
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 on # GPIO 6-9
irq 0x30 = 0x00
irq 0xe8 = 0xff
irq 0xea = 0xff
irq 0xf6 = 0xff
irq 0xf8 = 0xff
end
device pnp 2e.8 on # WDT1, GPIO0-1, GPIOA
irq 0x30 = 0x00
irq 0xe2 = 0xff
irq 0xf0 = 0xb0
irq 0xf1 = 0x01
end
device pnp 2e.9 on # GPIO2-5
irq 0x30 = 0xb6
irq 0xe0 = 0xff
irq 0xe6 = 0xff
irq 0xea = 0xff
end
device pnp 2e.a on # ACPI
irq 0xe3 = 0x01
irq 0xe4 = 0x10
irq 0xe6 = 0x4c
irq 0xf0 = 0x20
end
device pnp 2e.b on # HWM, front panel LED
irq 0x30 = 0xe1
io 0x60 = 0x290
end
device pnp 2e.d on end # VID
device pnp 2e.e off end # CIR wake-up
device pnp 2e.f on end # GPIO push-pull or open drain
device pnp 2e.14 on end # SVID
device pnp 2e.16 off # Deep Sleep
irq 0x30 = 0x68
end
device pnp 2e.17 off end # GPIOA
end
end
device ref sata1 on
subsystemid 0x1849 0x1e02
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f"
end
device ref smbus on
subsystemid 0x1849 0x1e22
end
end
end
end

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src/mainboard/asrock/z77_extreme4/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB)
{
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}

12
src/mainboard/asrock/z77_extreme4/early_init.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <bootblock_common.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/common/nuvoton.h>
void bootblock_mainboard_early_init(void)
{
/* Enable early serial */
if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(NCT6776_SP1, CONFIG_TTYS0_BASE);
}

17
src/mainboard/asrock/z77_extreme4/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI1, -- mainboard DVI port
HDMI3, -- mainboard HDMI port
Analog,
others => Disabled);
end GMA.Mainboard;

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src/mainboard/asrock/z77_extreme4/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_NATIVE,
.gpio3 = GPIO_MODE_NATIVE,
.gpio4 = GPIO_MODE_NATIVE,
.gpio5 = GPIO_MODE_NATIVE,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_NATIVE,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_NATIVE,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_NATIVE,
.gpio22 = GPIO_MODE_NATIVE,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio8 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio12 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_NATIVE,
.gpio36 = GPIO_MODE_NATIVE,
.gpio37 = GPIO_MODE_NATIVE,
.gpio38 = GPIO_MODE_NATIVE,
.gpio39 = GPIO_MODE_NATIVE,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_NATIVE,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_NATIVE,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_NATIVE,
.gpio51 = GPIO_MODE_NATIVE,
.gpio52 = GPIO_MODE_NATIVE,
.gpio53 = GPIO_MODE_NATIVE,
.gpio54 = GPIO_MODE_NATIVE,
.gpio55 = GPIO_MODE_NATIVE,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_NATIVE,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_NATIVE,
.gpio71 = GPIO_MODE_NATIVE,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio72 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

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src/mainboard/asrock/z77_extreme4/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
static const u32 realtek_alc898_verbs[] = {
AZALIA_SUBVENDOR(0, 0x18491898),
AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
AZALIA_PIN_CFG(0, 0x19, 0x02a19950),
AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
AZALIA_PIN_CFG(0, 0x1b, 0x02214120),
AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
AZALIA_PIN_CFG(0, 0x1e, 0x01451130),
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
};
static const u32 intel_display_audio_verbs[] = {
AZALIA_SUBVENDOR(3, 0x80860101),
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
AZALIA_PIN_CFG(3, 0x06, 0x58560020),
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[0] = {};
struct azalia_codec mainboard_azalia_codecs[] = {
{
.name = "Realtek ALC898",
.vendor_id = 0x10ec0899,
.subsystem_id = 0x18491898,
.address = 0,
.verbs = realtek_alc898_verbs,
.verb_count = ARRAY_SIZE(realtek_alc898_verbs),
},
{
.name = "Intel Display Audio (HDMI)",
.vendor_id = 0x80862806,
.subsystem_id = 0x80860101,
.address = 3,
.verbs = intel_display_audio_verbs,
.verb_count = ARRAY_SIZE(intel_display_audio_verbs),
},
{ /* terminator */ }
};
AZALIA_ARRAY_SIZES;

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src/mainboard/asrock/z77_extreme4/mainboard.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_CRT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};