mb/siemens/mc_rpl1: Document CLKSRC 2 usage for PCIe RP5

PCIe Root Port 5 uses both CLKSRC 1 and CLKSRC 2, but coreboot's
devicetree only allows configuring a single clock source per port. Add
a comment to document that CLKSRC 2 is implicitly used by the hardware.

Change-Id: I9b54d97fa5e4e4e80a58392a7592bab91e00824d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb

@@ -96,6 +96,7 @@ chip soc/intel/alderlake
 			}"
 		end
 		device ref pcie_rp5 on
+			# Uses CLKSRC 1 + 2 (only 1 configurable)
 			register "pch_pcie_rp[PCH_RP(5)]" = "{
 				.clk_src = 1,
 				.flags = PCIE_RP_CLK_REQ_UNUSED,