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mb/google/ocelot/var/matsu: Update GPIO table

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Configure GPIOs and related settings per schematic_20251028.

BUG=b:443612246
TEST=emerge-ocelot coreboot

Change-Id: I59227e435448eb6e362ab45d443fdea2f64a4233
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Ivy Jian 2025-10-30 12:26:53 +08:00 • committed by Matt DeVillier
commit 05c0e16593
1 changed files with 216 additions and 187 deletions
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403
src/mainboard/google/ocelot/variants/matsu/gpio.c
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@ -31,34 +31,38 @@ static const struct pad_config gpio_table[] = {
/* GPP_A08: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
/* GPP_A10: WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_A10, 1, PLTRST),
/* GPP_A11: WLAN_RST_N */
PAD_CFG_GPO(GPP_A11, 1, PLTRST),
/* GPP_A12: WIFI_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
/* GPP_A13: PCIE_LNK_DOWN */
PAD_CFG_NF_OWNERSHIP(GPP_A13, NONE, DEEP, NF2, ACPI),
/* GPP_A15: CODEC_GPIO_EN */
PAD_CFG_GPO(GPP_A15, 1, DEEP),
/* GPP_A09: NC */
PAD_NC(GPP_A09, NONE),
/* GPP_A10: NC */
PAD_NC(GPP_A10, NONE),
/* GPP_A11: NC */
PAD_NC(GPP_A11, NONE),
/* GPP_A12: NC */
PAD_NC(GPP_A12, NONE),
/* GPP_A13: NC */
PAD_NC(GPP_A13, NONE),
/* GPP_A15: NC */
PAD_NC(GPP_A15, NONE),
/* GPP_B */
/* GPP_B00: USBC_SML_CLK_PD */
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
/* GPP_B01: USBC_SML_DATA_PD */
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
/* GPP_B02: NC */
PAD_NC(GPP_B02, NONE),
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
/* GPP_B03: NC */
PAD_NC(GPP_B03, NONE),
/* GPP_B04: ISH_GP_0_SNSR_HDR */
/* GPP_B04: NC */
PAD_NC(GPP_B04, NONE),
/* GPP_B06: SOC_PDB_CTRL */
PAD_CFG_GPO(GPP_B06, 0, DEEP),
/* GPP_B08: ISH_GP_4_SNSR_HDR */
PAD_NC(GPP_B08, NONE),
/* GPP_B05: EC_ISH_INT_ODL */
PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
/* GPP_B06: MEM_STRAP_2 */
PAD_CFG_GPI(GPP_B06, NONE, DEEP),
/* GPP_B07: NC */
PAD_NC(GPP_B07, NONE),
/* GPP_B08: MEM_STRAP_3 */
PAD_CFG_GPI(GPP_B08, NONE, DEEP),
/* GPP_B09: BT_RF_KILL_N */
PAD_CFG_GPO(GPP_B09, 1, DEEP),
/* GPP_B10: NC */
@ -69,30 +73,38 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B14: GPP_B14_DDSP_HPDB */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
/* GPP_B16: COINLESS_MODE_SELECT */
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_B20: WWAN_RST_N */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B24: ESPI_ALERT0_EC_R_N */
/* GPP_B16: NC */
PAD_NC(GPP_B16, NONE),
/* GPP_B17: NC */
PAD_NC(GPP_B17, NONE),
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
/* GPP_B20: NC */
PAD_NC(GPP_B20, NONE),
/* GPP_B21: NC */
PAD_NC(GPP_B21, NONE),
/* GPP_B22: ISH_GP_5_SNSR_HDR */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
/* GPP_B23: NC */
PAD_NC(GPP_B23, NONE),
/* GPP_B24: NC */
PAD_NC(GPP_B24, NONE),
/* GPP_B25: None */
/* GPP_B25: NC */
PAD_NC(GPP_B25, NONE),
/* GPP_C */
/* GPP_C00: SPD_SMB_CLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SPD_SMB_DATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C00: MIC_PWR_EN */
PAD_CFG_GPO(GPP_C00, 1, DEEP),
/* GPP_C01: EN_FCAM_PWR */
PAD_CFG_GPO(GPP_C01, 1, DEEP),
/* GPP_C02: NC */
PAD_NC(GPP_C02, NONE),
/* GPP_C03: TCP_LAN_SML0_SCL_R */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
/* GPP_C04: TCP_LAN_SML0_SDA_R */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
/* GPP_C03: NC */
PAD_NC(GPP_C03, NONE),
/* GPP_C04: NC */
PAD_NC(GPP_C04, NONE),
/* GPP_C05: NC */
PAD_NC(GPP_C05, NONE),
/* GPP_C06: NC */
@ -101,102 +113,106 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C07, NONE),
/* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */
PAD_CFG_GPO(GPP_C08, 1, PLTRST),
/* GPP_C09: CLKREQ0_X1_GEN4_M2_WLAN_N */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
/* GPP_C09: NC */
PAD_NC(GPP_C09, NONE),
/* GPP_C10: WIFI_RF_KILL_N */
PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* GPP_C11: CLKREQ2_X4_GEN4_DT_CEM_SLOT1_N */
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
/* GPP_C11: NC */
PAD_NC(GPP_C11, NONE),
/* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C13: CLKREQ4_X4_GEN4_DT_CEM_SLOT2_N */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
/* GPP_C14: CLKREQ5_X1_GEN1_GBE_LAN_N */
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
/* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* GPP_C13: NC */
PAD_NC(GPP_C13, NONE),
/* GPP_C14: NC */
PAD_NC(GPP_C14, NONE),
/* GPP_C15: NC */
PAD_NC(GPP_C15, NONE),
/* GPP_C16: NC */
PAD_NC(GPP_C16, NONE),
/* GPP_C17: NC */
PAD_NC(GPP_C17, NONE),
/* GPP_C18: NC */
PAD_NC(GPP_C18, NONE),
/* GPP_C19: NC */
PAD_NC(GPP_C19, NONE),
/* GPP_C22: DDPB_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
/* GPP_C23: DDPB_HDMI_CTRLDATA */
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
/* GPP_D */
/* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */
PAD_CFG_GPO(GPP_D01, 1, DEEP),
/* GPP_D01: NC */
PAD_NC(GPP_D01, NONE),
/* GPP_D02: SOC_WP_OD */
PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_D03: X4_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
/* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */
PAD_CFG_GPI(GPP_D02, NONE, DEEP),
/* GPP_D03: NC */
PAD_NC(GPP_D03, NONE),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
/* GPP_D07: NC */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */
/* GPP_D08: NC */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: I2S_MCLK_HDR */
PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
/* GPP_D10: HDA_BCLK (HDR) */
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
/* GPP_D11: HDA_SYNC (HDR) */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
/* GPP_D12: HDA_SDO (HDR) */
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
/* GPP_D13: HDA_SDI0 (HDR) */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* GPP_D16: HDA_RST_N (HDR) */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
/* GPP_D17: HDA_SDI1 (HDR) */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* GPP_D19: NC */
PAD_NC(GPP_D19, NONE),
/* GPP_D21: GPP_D21_UFS_REFCLK_R */
/* GPP_D09: NC */
PAD_NC(GPP_D09, NONE),
/* GPP_D10: NC */
PAD_NC(GPP_D10, NONE),
/* GPP_D11: NC */
PAD_NC(GPP_D11, NONE),
/* GPP_D12: NC */
PAD_NC(GPP_D12, NONE),
/* GPP_D13: NC */
PAD_NC(GPP_D13, NONE),
/* GPP_D16: DMIC_CLK_A1 */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
/* GPP_D17: DMIC_DATA_1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
/* GPP_D19: TCHSCR_RPT_EN */
PAD_CFG_GPO(GPP_D19, 0, PLTRST),
/* GPP_D21: GPP_D21_UFS_REFCLK */
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
/* GPP_E */
/* GPP_E01: PM_SLP_DRAM_N */
PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
/* GPP_E01: NC */
PAD_NC(GPP_E01, NONE),
/* GPP_E02: NC */
PAD_NC(GPP_E02, NONE),
/* GPP_E03: X4_DT_PCIE_RST_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E03: NC */
PAD_NC(GPP_E03, NONE),
/* GPP_E05: GPP_E5_FPS_PWREN */
PAD_CFG_GPO(GPP_E05, 1, DEEP),
/* GPP_E06: GPP_E6_PEN_DETECT */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, LEVEL, ACPI),
/* GPP_E07: LAN_GPIO_RST_N */
PAD_CFG_GPO(GPP_E07, 1, PLTRST),
/* GPP_E06: NC */
PAD_NC(GPP_E06, NONE),
/* GPP_E07: NC */
PAD_NC(GPP_E07, NONE),
/* GPP_E08: EC_SOC_INT_ODL */
PAD_CFG_GPI(GPP_E08, NONE, DEEP),
/* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */
PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E09: USB_A_OC_ODL */
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
/* GPP_E10: M2_UFS_DET_SEL_N */
PAD_CFG_GPI(GPP_E10, NONE, DEEP),
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
/* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
/* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
/* GPP_E17: GPP_E17_GSPI0A_CS0 */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
/* GPP_E19: FPS_INT_N */
PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
/* GPP_E20: FPS_FW_UPDATE */
PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
/* GPP_E10: NC */
PAD_NC(GPP_E10, NONE),
/* GPP_E11: NC */
PAD_NC(GPP_E11, NONE),
/* GPP_E12: I2C_TCHPAD_SCL */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
/* GPP_E13: I2C_TCHPAD_SDA */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
/* GPP_E14: GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E14, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E15: NC */
PAD_NC(GPP_E15, NONE),
/* GPP_E16: NC */
PAD_NC(GPP_E16, NONE),
/* GPP_E17: NC */
PAD_NC(GPP_E17, NONE),
/* GPP_E18: TCHPAD_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E19: NC */
PAD_NC(GPP_E19, NONE),
/* GPP_E20: NC */
PAD_NC(GPP_E20, NONE),
/* GPP_E21: I2C_PMC_PD_INT_N */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* GPP_E22: NC */
@ -215,86 +231,105 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
/* GPP_F05: CRF_CLKREQ_R */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
/* GPP_F06: DISC_WLAN_WWAN_COEX3 */
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
/* GPP_F07: FUSA_DIAGTEST_EN_HDR */
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
/* GPP_F08: TCH_PNL1_PWR_EN */
/* GPP_F06: NC */
PAD_NC(GPP_F06, NONE),
/* GPP_F07: NC */
PAD_NC(GPP_F07, NONE),
/* GPP_F08: TCHSCR_PNL1_PWR_EN */
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
/* GPP_F09: M2_UFS_RST_N */
PAD_CFG_GPO(GPP_F09, 1, DEEP),
/* GPP_F10: X4_PCIE_SLOT1_PWR_EN */
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
/* GPP_F11: THC1_SPI2_CLK_TCH_PNL2 */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF11),
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
/* GPP_F10: ISH_ACCEL_MB_INT_L*/
PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
/* GPP_F11: NC */
PAD_NC(GPP_F11, NONE),
/* GPP_F12: TCHSCR_I2C5_SCL */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
/* GPP_F13: TCHSCR_I2C5_SDA */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
/* GPP_F14: GPP_F14_GPSI0A_MOSI */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15: GPP_F15_GSPI0A_MISO */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16: GPP_F16_GSPI0A_CLK */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F17: CODEC_IRQ_HDR */
PAD_CFG_GPI(GPP_F17, NONE, DEEP),
/* GPP_F18: TCH_PAD_INT_N */
PAD_CFG_GPI_APIC_DRIVER(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
/* GPP_F14: NC */
PAD_NC(GPP_F14, NONE),
/* GPP_F15: NC */
PAD_NC(GPP_F15, NONE),
/* GPP_F16: SOC_TCHSCR_INT */
PAD_CFG_GPI_APIC(GPP_F16, NONE, PLTRST, LEVEL, NONE),
/* GPP_F17: NC */
PAD_NC(GPP_F17, NONE),
/* GPP_F18: TCHSCR_RST_L */
PAD_CFG_GPO(GPP_F18, 1, DEEP),
/* GPP_F19: NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: CSE_EARLY_SW */
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
/* GPP_F22: THC1_SPI2_DSYNC */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
/* GPP_F22: NC */
PAD_NC(GPP_F22, NONE),
/* GPP_F23: NC */
PAD_NC(GPP_F23, NONE),
/* GPP_H */
/* GPP_H00: NC */
PAD_NC(GPP_H00, NONE),
/* GPP_H01: M2_UFS_SLP_N */
PAD_CFG_GPO(GPP_H01, 1, DEEP),
/* GPP_H02: DEBUG_TRACE_PNP */
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
/* GPP_H03: MIC MUTE */
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
/* GPP_H04: CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
/* GPP_H05: CNV_MFUART2_TXD */
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
/* GPP_H06: I2C3_SCL_AUDIO_HDR */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SDA_AUDIO_HDR */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_H01: NC */
PAD_NC(GPP_H01, NONE),
/* GPP_H02: NC */
PAD_NC(GPP_H02, NONE),
/* GPP_H03: NC */
PAD_NC(GPP_H03, NONE),
/* GPP_H04: NC */
PAD_NC(GPP_H04, NONE),
/* GPP_H05: NC */
PAD_NC(GPP_H05, NONE),
/* GPP_H06: NC */
PAD_NC(GPP_H06, NONE),
/* GPP_H07: NC */
PAD_NC(GPP_H07, NONE),
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10: UART0_BUF_RTS */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
/* GPP_H11: UART0_BUF_CTS */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
/* GPP_H10: NC */
PAD_NC(GPP_H10, NONE),
/* GPP_H11: NC */
PAD_NC(GPP_H11, NONE),
/* GPP_H13: NC */
PAD_NC(GPP_H13, NONE),
/* GPP_H14: NC */
PAD_NC(GPP_H14, NONE),
/* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */
/* GPP_H15: NC */
PAD_NC(GPP_H15, NONE),
/* GPP_H17: MIC MUTE LED */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* GPP_H17: NC */
PAD_NC(GPP_H17, NONE),
/* GPP_H18: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_H18, 1, DEEP),
/* GPP_H19: I3C0_SDA_HDR */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
/* GPP_H20: I3C0_SCL_HDR */
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
/* GPP_H21: I2C1_SDA_TTK_CHROME */
/* GPP_H19: NC */
PAD_NC(GPP_H19, NONE),
/* GPP_H20: NC */
PAD_NC(GPP_H20, NONE),
/* GPP_H21: SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_TTK_CHROME */
/* GPP_H22: SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* GPP_H23: TP */
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
/* GPP_H24: TP */
PAD_CFG_NF(GPP_H24, NONE, DEEP, NF1),
/* GPP_H23: MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
/* GPP_H24: MEM_STRAP_1 */
PAD_CFG_GPI(GPP_H24, NONE, DEEP),
/* GPP_S00: SNDW3_CLK_CODEC */
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
/* GPP_S01: SNDW3_DATA0_CODEC */
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
/* GPP_S02: SNDW3_DATA1_CODEC */
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
/* GPP_S03: SNDW3_DATA2_CODEC */
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
/* GPP_S04: DMIC_CLK_A0 */
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
/* GPP_S05: DMIC_DATA_0 */
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
/* GPP_S06: NC */
PAD_NC(GPP_S06, NONE),
/* GPP_S07: NC */
PAD_NC(GPP_S07, NONE),
/* GPP_V */
/* GPP_V00: PM_BATLOW_N */
@ -313,14 +348,14 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
/* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
/* GPP_V08: SLP_WLAN_N */
/* GPP_V08: RSVD */
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
/* GPP_V09: PM_SLP_S5_N */
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
/* GPP_V10: LANPHYPC_R_N */
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
/* GPP_V11: PM_SLP_LAN_N */
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
/* GPP_V10: NC */
PAD_NC(GPP_V10, NONE),
/* GPP_V11: NC */
PAD_NC(GPP_V11, NONE),
/* GPP_V12: WAKE_N */
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
/* GPP_V13: GPP_V13_CATERR_N */
@ -335,30 +370,24 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
/* GPP_H06: I2C3_SDA_PSS */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SCL_PSS */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_E14: GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E14, NONE, PLTRST, LEVEL, INVERT),
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H21: I2C1_SDA_TTK_CHROME */
/* GPP_H21: SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_TTK_CHROME */
/* GPP_H22: SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
};
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_C00: SPD_SMB_CLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SPD_SMB_DATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
/* GPP_H18: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_H18, 1, PLTRST),
/* GPP_A08: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
};
const struct pad_config *variant_gpio_table(size_t *num)