mb/google/brox/var/caboc: Adjust WWAN power off sequence

Currently wwan_power.asl clears gpio WWAN (PERST) during power-off.

Caboc project uses a MOS reverse pin to connect GPP_A21
(WWAN_ASPM_EXIT) to WWAN (PERST). Based on this design, uses STXS to
keep GPP_A21 high to meet power-off sequence.

Set T1_OFF_MS to 20ms and T2_OFF_MS to 10ms as HW engineer requested.

BUG=b:453512678
TEST=emerge-brox coreboot
     HW enginer has measured and confirms WWAN power-off sequence.

Change-Id: I202a370dba2ba1dec61b1ad44140674bd470ba6e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

src/mainboard/google/brox/Kconfig

@@ -100,7 +100,6 @@ config BOARD_GOOGLE_CABOC
 	select BOARD_GOOGLE_BASEBOARD_BROX
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_WWAN_FM350GL
-	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
 	select RT8168_GEN_ACPI_POWER_RESOURCE

src/mainboard/google/brox/variants/caboc/include/variant/gpio.h

@@ -5,8 +5,8 @@
 
 #include <baseboard/gpio.h>
 
-#define T1_OFF_MS	16
-#define T2_OFF_MS	2
+#define T1_OFF_MS	20
+#define T2_OFF_MS	10
 #define WWAN_FCPO	GPP_F21
 #define WWAN_RST	GPP_D19
 #define WWAN_PERST	GPP_A21

src/mainboard/google/brox/wwan_power.asl

@@ -7,6 +7,10 @@ Method (MPTS, 1)
 #if CONFIG(HAVE_PCIE_WWAN)
 	\_SB.PCI0.CTXS(WWAN_PERST);
 	Sleep(T1_OFF_MS)
+#endif
+#if CONFIG(BOARD_GOOGLE_CABOC)
+	\_SB.PCI0.STXS(WWAN_PERST);
+	Sleep(T1_OFF_MS)
 #endif
 	\_SB.PCI0.CTXS(WWAN_RST);
 	Sleep(T2_OFF_MS)