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mb/google/ocelot: Create kodkod variant

Browse source 
Create the kodkod variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.

BUG=b:451760650
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_KODKOD

Change-Id: I8bbea4444d65e57b98bf9c8a621ff548abb8aece
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89679
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ian Feng 2025-10-22 12:00:32 +08:00 • committed by Matt DeVillier
commit aab8ad98b6
10 changed files with 603 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

20
src/mainboard/google/ocelot/Kconfig
View file

@ -28,7 +28,7 @@ config BOARD_GOOGLE_OCELOT_COMMON
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select HAVE_SPD_IN_CBFS if !BOARD_GOOGLE_MODEL_KODKOD
select I2C_TPM
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_DISABLE_STAGE_CACHE
@ -50,13 +50,22 @@ config BOARD_GOOGLE_BASEBOARD_OCELOT
select DRIVERS_INTEL_USB4_RETIMER
select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS
select MEMORY_SOLDERDOWN
select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_MODEL_KODKOD
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SYSTEM_TYPE_LAPTOP
select TPM_GOOGLE_TI50
config BOARD_GOOGLE_MODEL_KODKOD
def_bool n
select BOARD_GOOGLE_BASEBOARD_OCELOT
select FSP_UGOP_EARLY_SIGN_OF_LIFE
select EC_GOOGLE_CHROMEEC_RTK
select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
select SPD_CACHE_ENABLE
select SPD_CACHE_IN_FMAP
config BOARD_GOOGLE_MODEL_MATSU
def_bool n
select BOARD_GOOGLE_BASEBOARD_OCELOT
@ -81,6 +90,9 @@ config BOARD_GOOGLE_MODEL_OJAL
select EC_GOOGLE_CHROMEEC_RTK
select EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
config BOARD_GOOGLE_KODKOD
select BOARD_GOOGLE_MODEL_KODKOD
config BOARD_GOOGLE_MATSU
select BOARD_GOOGLE_MODEL_MATSU
@ -140,6 +152,7 @@ config DRIVER_TPM_I2C_ADDR
config DRIVER_TPM_I2C_BUS
hex
default 0x01 if BOARD_GOOGLE_MODEL_KODKOD
default 0x01 if BOARD_GOOGLE_MODEL_MATSU
default 0x01 if BOARD_GOOGLE_MODEL_OCELOT
default 0x01 if BOARD_GOOGLE_MODEL_OJAL
@ -155,6 +168,7 @@ config MAINBOARD_FAMILY
default "Google_Ocelot"
config MAINBOARD_PART_NUMBER
default "Kodkod" if BOARD_GOOGLE_MODEL_KODKOD
default "Matsu" if BOARD_GOOGLE_MODEL_MATSU
default "Ocelot" if BOARD_GOOGLE_MODEL_OCELOT
default "Ojal" if BOARD_GOOGLE_OJAL
@ -166,6 +180,7 @@ config MEMORY_SOLDERDOWN
config TPM_TIS_ACPI_INTERRUPT
int
default 49 if BOARD_GOOGLE_MODEL_KODKOD # GPE0_DW1_17 (GPP_B17)
default 78 if BOARD_GOOGLE_MODEL_MATSU # GPE0_DW2_14 (GPP_E14)
default 49 if BOARD_GOOGLE_MODEL_OCELOT # GPE0_DW1_17 (GPP_B17)
default 49 if BOARD_GOOGLE_MODEL_OJAL # GPE0_DW1_17 (GPP_B17)
@ -179,6 +194,7 @@ config USE_PM_ACPI_TIMER
config VARIANT_DIR
string
default "kodkod" if BOARD_GOOGLE_MODEL_KODKOD
default "matsu" if BOARD_GOOGLE_MODEL_MATSU
default "ocelot" if BOARD_GOOGLE_MODEL_OCELOT
default "ojal" if BOARD_GOOGLE_MODEL_OJAL

3
src/mainboard/google/ocelot/Kconfig.name
View file

@ -2,6 +2,9 @@
comment "Ocelot"
config BOARD_GOOGLE_KODKOD
bool "-> Kodkod"
config BOARD_GOOGLE_MATSU
bool "-> Matsu"

2
src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h
View file

@ -15,6 +15,8 @@
//TODO for Nuvo: #define EC_SYNC_IRQ GPP_E07_IRQ
#if CONFIG(BOARD_GOOGLE_MODEL_OCELOT) || CONFIG(BOARD_GOOGLE_MODEL_OJAL)
#define EC_SYNC_IRQ 0 /* Not Connected */
#elif CONFIG(BOARD_GOOGLE_MODEL_KODKOD)
#define EC_SYNC_IRQ GPP_F10_IRQ
#elif CONFIG(BOARD_GOOGLE_MODEL_MATSU)
#define EC_SYNC_IRQ GPP_E08_IRQ
#endif

6
src/mainboard/google/ocelot/variants/kodkod/Makefile.mk Normal file
View file

@ -0,0 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c

393
src/mainboard/google/ocelot/variants/kodkod/gpio.c Normal file
View file

@ -0,0 +1,393 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* GPP_A */
/* GPP_A00: ESPI_IO0_AIC */
/* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
/* GPP_A01: ESPI_IO1_AIC */
/* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
/* GPP_A02: ESPI_IO2_AIC */
/* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
/* GPP_A03: ESPI_IO3_AIC */
/* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
/* GPP_A04: ESPI_CS0_AIC_N */
/* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
/* GPP_A05: ESPI_CLK_AIC */
/* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
/* GPP_A06: ESPI_RST_AIC_N */
/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
/* GPP_A08: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_A08, 1, PLTRST),
/* GPP_A09: NC */
PAD_NC(GPP_A09, NONE),
/* GPP_A10: NC */
PAD_NC(GPP_A10, NONE),
/* GPP_A11: NC */
PAD_NC(GPP_A11, NONE),
/* GPP_A12: NC */
PAD_NC(GPP_A12, NONE),
/* GPP_A13: TCH_PAD_INT_N */
PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT),
/* GPP_A15: NC */
PAD_NC(GPP_A15, NONE),
/* GPP_B */
/* GPP_B00: USBC_SML_CLK_PD */
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
/* GPP_B01: USBC_SML_DATA_PD */
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
PAD_NC(GPP_B02, NONE),
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
PAD_NC(GPP_B03, NONE),
/* GPP_B04: ISH_GP_0_SNSR_HDR */
PAD_NC(GPP_B04, NONE),
/* GPP_B06: SOC_PDB_CTRL */
PAD_CFG_GPO(GPP_B06, 0, DEEP),
/* GPP_B08: NC */
PAD_NC(GPP_B08, NONE),
/* GPP_B09: BT_RF_KILL_N */
PAD_CFG_GPO(GPP_B09, 1, DEEP),
/* GPP_B10: NC */
PAD_NC(GPP_B10, NONE),
/* GPP_B12: PM_SLP_S0_N */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* GPP_B13: PLT_RST_N */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B14: GPP_B14_DDSP_HPDB */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
/* GPP_B16: NC */
PAD_NC(GPP_B16, NONE),
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_B20: SOC_KB_MATRIX */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B22: SOC_CAM_WP */
PAD_CFG_GPO(GPP_B22, 0, DEEP),
/* GPP_B24: ESPI_ALERT0_EC_R_N */
PAD_NC(GPP_B24, NONE),
/* GPP_B25: None */
PAD_NC(GPP_B25, NONE),
/* GPP_C */
/* GPP_C00: SPD_SMB_CLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SPD_SMB_DATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C02: NC */
PAD_NC(GPP_C02, NONE),
/* GPP_C03: TCP_LAN_SML0_SCL_R */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
/* GPP_C04: TCP_LAN_SML0_SDA_R */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
/* GPP_C05: NC */
PAD_NC(GPP_C05, NONE),
/* GPP_C06: NC */
PAD_NC(GPP_C06, NONE),
/* GPP_C07: NC */
PAD_NC(GPP_C07, NONE),
/* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */
PAD_CFG_GPO(GPP_C08, 1, PLTRST),
/* GPP_C09: NC */
PAD_NC(GPP_C09, NONE),
/* GPP_C10: WIFI_RF_KILL_N */
PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* GPP_C11: NC */
PAD_NC(GPP_C11, NONE),
/* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C13: NC */
PAD_NC(GPP_C13, NONE),
/* GPP_C14: NC */
PAD_NC(GPP_C14, NONE),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
/* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* GPP_C22: DDPB_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
/* GPP_C23: DDPB_HDMI_CTRLDATA */
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
/* GPP_D */
/* GPP_D01: NC */
PAD_NC(GPP_D01, NONE),
/* GPP_D02: SOC_WP_OD */
PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_D03: NC */
PAD_NC(GPP_D03, NONE),
/* GPP_D07: NC */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: NC */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: NC */
PAD_NC(GPP_D09, NONE),
/* GPP_D10: NC */
PAD_NC(GPP_D10, NONE),
/* GPP_D11: NC */
PAD_NC(GPP_D11, NONE),
/* GPP_D12: NONE */
PAD_NC(GPP_D12, NONE),
/* GPP_D13: NC */
PAD_NC(GPP_D13, NONE),
/* GPP_D16: NC */
PAD_NC(GPP_D16, NONE),
/* GPP_D17: NC */
PAD_NC(GPP_D17, NONE),
/* GPP_D19: NC */
PAD_NC(GPP_D19, NONE),
/* GPP_D21: GPP_D21_UFS_REFCLK_R */
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
/* GPP_E */
/* GPP_E01: PM_SLP_DRAM_N */
PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2),
/* GPP_E02: VR_ALERT#_R */
PAD_NC(GPP_E02, NONE),
/* GPP_E03: NC */
PAD_NC(GPP_E03, NONE),
/* GPP_E05: NC */
PAD_NC(GPP_E05, NONE),
/* GPP_E06: CAM_PRIVACY */
PAD_CFG_GPO(GPP_E06, 1, DEEP),
/* GPP_E07: NC */
PAD_NC(GPP_E07, NONE),
/* GPP_E08: NC */
PAD_NC(GPP_E08, NONE),
/* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
/* GPP_E10: NONE */
PAD_NC(GPP_E10, NONE),
/* GPP_E11: NC */
PAD_NC(GPP_E11, NONE),
/* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
/* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
/* GPP_E14: NC */
PAD_NC(GPP_E14, NONE),
/* GPP_E15: NC */
PAD_NC(GPP_E15, NONE),
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
/* GPP_E17: NC */
PAD_NC(GPP_E17, NONE),
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
/* GPP_E19: FPS_INT_N */
PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT),
/* GPP_E20: FPS_FW_UPDATE */
PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
/* GPP_E21: I2C_PMC_PD_INT_N */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* GPP_E22: NC */
PAD_NC(GPP_E22, NONE),
/* GPP_F */
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
/* GPP_F04: CNV_RF_RESET_R_N */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
/* GPP_F05: CRF_CLKREQ_R */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
/* GPP_F06: NC */
PAD_NC(GPP_F06, NONE),
/* GPP_F07: NC */
PAD_NC(GPP_F07, NONE),
/* GPP_F08: TCH_PNL1_PWR_EN */
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
/* GPP_F09: M2_UFS_RST_N */
PAD_CFG_GPO(GPP_F09, 1, DEEP),
/* GPP_F10: SOC_EC_INT */
PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F11: NC */
PAD_NC(GPP_F11, NONE),
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
/* GPP_F14: GPP_F14_GPSI0A_MOSI */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15: GPP_F15_GSPI0A_MISO */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16: GPP_F16_GSPI0A_CLK */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
/* GPP_F17: NC */
PAD_NC(GPP_F17, NONE),
/* GPP_F18: GPP_F18_GSPI0A_CS0 */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
/* GPP_F19: NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: CSE_EARLY_SW */
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
/* GPP_F22: THC1_SPI2_DSYNC */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
/* GPP_H */
/* GPP_H00: NC */
PAD_NC(GPP_H00, NONE),
/* GPP_H01: M2_UFS_SLP_N */
PAD_CFG_GPO(GPP_H01, 1, DEEP),
/* GPP_H02: DEBUG_TRACE_PNP */
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
/* GPP_H03: MIC MUTE */
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
/* GPP_H04: NC */
PAD_NC(GPP_H04, NONE),
/* GPP_H05: NC */
PAD_NC(GPP_H05, NONE),
/* GPP_H06: I2C3_SCL_AUDIO_HDR */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SDA_AUDIO_HDR */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10: NC */
PAD_NC(GPP_H10, NONE),
/* GPP_H11: NC */
PAD_NC(GPP_H11, NONE),
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
PAD_NC(GPP_H14, NONE),
/* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */
PAD_NC(GPP_H15, NONE),
/* GPP_H17: MIC MUTE LED */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* GPP_H18: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_H18, 1, DEEP),
/* GPP_H19: I3C0_SDA_HDR */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
/* GPP_H20: I3C0_SCL_HDR */
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
/* GPP_H21: I2C1_SDA_TTK_CHROME */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_TTK_CHROME */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* GPP_H23: NC */
PAD_NC(GPP_H23, NONE),
/* GPP_H24: NC */
PAD_NC(GPP_H24, NONE),
/* GPP_V */
/* GPP_V00: PM_BATLOW_N */
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
/* GPP_V01: BC_ACOK_MCP */
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
/* GPP_V02: LANWAKE_N_R */
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
/* GPP_V03: PWRBTN_MCP_N */
PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1),
/* GPP_V04: PM_SLP_S3_N */
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
/* GPP_V05: PM_SLP_S4_N */
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
/* GPP_V06: PM_SLP_A_N */
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
/* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
/* GPP_V08: SLP_WLAN_N */
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
/* GPP_V09: PM_SLP_S5_N */
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
/* GPP_V10: NC */
PAD_NC(GPP_V10, NONE),
/* GPP_V11: PM_SLP_LAN_N */
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
/* GPP_V12: WAKE_N */
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
/* GPP_V13: GPP_V13_CATERR_N */
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
/* GPP_V14: GPP_V14_FORCEPR_N */
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
/* GPP_V15: GPP_V15_THERMTRIP_N */
PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
/* GPP_V16: GPP_V16_VCCST_EN */
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT),
/* GPP_H06: I2C3_SDA_PSS */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SCL_PSS */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H21: I2C1_SDA_TTK_CHROME */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_TTK_CHROME */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
};
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_C00: SPD_SMB_CLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: SPD_SMB_DATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
};
const struct pad_config *variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* Create the stub for romstage gpio, typically use for power sequence */
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
};
DECLARE_CROS_GPIOS(cros_gpios);

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src/mainboard/google/ocelot/variants/kodkod/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
0x10ec12ac, /* Subsystem ID */
0x00000013, /* Number of jacks (NID entries) */
AZALIA_RESET(0x1),
/* NID 0x01, HDA Codec Subsystem ID Verb Table */
AZALIA_SUBVENDOR(0, 0x10ec12ac),
/* Pin Widget Verb Table */
/*
* DMIC
* Requirement is to use PCH DMIC. Hence,
* commented out codec's Internal DMIC.
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
*/
/* Pin widget 0x14 - Front (Port-D) */
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
/* Pin widget 0x18 - NPC */
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
/* Pin widget 0x19 - MIC2 (Port-F) */
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
/* Pin widget 0x1A - LINE1 (Port-C) */
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
/* Pin widget 0x1B - NPC */
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
/* Pin widget 0x1D - BEEP-IN */
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
/* Pin widget 0x1E - NPC */
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
/* Pin widget 0x21 - HP1-OUT (Port-I) */
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
/*
* Widget node 0x20 - 1
* Codec hidden reset and speaker power 2W/4ohm
*/
0x0205001A,
0x0204C003,
0x02050038,
0x02047901,
/*
* Widget node 0x20 - 2
* Class D power on Reset
*/
0x0205003C,
0x02040354,
0x0205003C,
0x02040314,
/*
* Widget node 0x20 - 3
* Disable AGC and set AGC limit to -1.5dB
*/
0x02050016,
0x02040C50,
0x02050012,
0x0204EBC1,
/*
* Widget node 0x20 - 4
* Set AGC Post gain +1.5dB then Enable AGC
*/
0x02050013,
0x02044023,
0x02050016,
0x02040E50,
/*
* Widget node 0x20 - 5
* Silence detector enabling + Set EAPD to verb control
*/
0x02050037,
0x0204FE15,
0x02050010,
0x02040020,
/*
* Widget node 0x20 - 6
* Silence data mode Threshold (-90dB)
*/
0x02050030,
0x0204A000,
0x0205001B,
0x02040A4B,
/*
* Widget node 0x20 - 7
* Default setting-1
*/
0x05750003,
0x05740DA3,
0x02050046,
0x02040004,
/*
* Widget node 0x20 - 8
* support 1 pin detect two port
*/
0x02050009,
0x0204E003,
0x0205000A,
0x02047770,
/*
* Widget node 0x20 - 9
* To set LDO1/LDO2 as default
*/
0x02050008,
0x02046A0C,
0x02050008,
0x02046A0C,
};
const u32 pc_beep_verbs[] = {
/* Dos beep path - 1 */
0x01470C00,
0x02050036,
0x02047151,
0x01470740,
/* Dos beep path - 2 */
0x0143b000,
0x01470C02,
0x01470C02,
0x01470C02,
};
AZALIA_ARRAY_SIZES;

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src/mainboard/google/ocelot/variants/kodkod/include/variant/ec.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif /* MAINBOARD_GPIO_H */

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src/mainboard/google/ocelot/variants/kodkod/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_GPIO_H__
#define __MAINBOARD_GPIO_H__
#include <baseboard/gpio.h>
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __MAINBOARD_GPIO_H__ */

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src/mainboard/google/ocelot/variants/kodkod/memory.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <boardid.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#define SMBUS_ADDR_DIMM 0x50
static const struct mb_cfg ddr5_mem_config = {
.type = MEM_TYPE_DDR5,
.ect = true, /* Early Command Training */
.user_bd = BOARD_TYPE_ULT_ULX,
.ddr_config = {
.dq_pins_interleaved = false,
},
};
const struct mb_cfg *variant_memory_params(void)
{
return &ddr5_mem_config;
}
void variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_DIMM_MODULE;
spd_info->smbus[0].addr_dimm[0] = SMBUS_ADDR_DIMM;
spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
}

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src/mainboard/google/ocelot/variants/kodkod/overridetree.cb Normal file
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chip soc/intel/pantherlake
device domain 0 on
end
end