mainboard/fatcat/lapis: Override PMC GPE configuration

Set the GPE0 registers (DW0, DW1, and DW2) to configure General
Purpose Events (GPEs) for the Lapis variant. This configures
GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups.

This patch ensures the variant can override the default baseboard
(fatcat) GPE settings, which may not align with the variant's
(aka lapis) hardware.

BUG=b:414614106
TEST=Able to override PMC GPEs as per google/lapis configuration.

Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>

src/mainboard/google/fatcat/variants/lapis/overridetree.cb

@@ -37,6 +37,10 @@ fw_config
 end
 
 chip soc/intel/pantherlake
+	# GPE configuration override
+	register "pmc_gpe0_dw0" = "GPP_VGPIO"
+	register "pmc_gpe0_dw1" = "GPP_F"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	register "power_limits_config[PTL_CORE_1]" = "{
 		.tdp_pl1_override = 15,