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mb/siemens/mc_rpl1: Disable I2C1 and enable I2C6

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Reconfigure I2C controller settings to disable I2C1 and enable I2C6
for the mc_rpl1 mainboard. This change reflects the updated hardware
configuration requirements.

Changes:
- Disable I2C controller 1
- Enable I2C controller 6

TEST=Build and boot tested on mc_rpl1 mainboard.
     Verified I2C6 functionality and confirmed I2C1 is disabled with
     `lspci -v | grep -A 5 "Serial bus controller"`. The output
     confirms that I2C6 (PCI 00:10.0) is enabled and I2C1 (PCI 00:15.1)
     is disabled because it is absent.

     ```
     00:10.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #2 (rev 01)
        Subsystem: Intel Corporation Alder Lake-P Serial IO I2C Controller
        Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 4
        Memory at 80a12000 (64-bit, non-prefetchable) [size=4K]
        Capabilities: [80] Power Management version 3
        Capabilities: [90] Vendor Specific Information: Len=14 <?>
     ```

Change-Id: I4867062743ee10b34f94a1e588a10115b553a16e
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kilian Krause 2025-10-23 13:16:51 +02:00 • committed by Matt DeVillier
commit 3ffb01e9cb
2 changed files with 6 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/gpio.c
View file

@ -30,8 +30,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_H1, NONE, PLTRST),
PAD_CFG_GPI(GPP_H2, NONE, PLTRST),
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C1_SDA */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C1_SCL */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* PCIE_XCLKREQ4 */
@ -44,6 +42,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* PCIE_XCLKREQ3 */
PAD_CFG_GPI(GPP_D10, NONE, PLTRST),
PAD_CFG_GPI(GPP_D12, NONE, PLTRST),
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), /* I2C6_SDA */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), /* I2C6_SCL */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* UART1_RXD */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* UART1_TXD */

7
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
View file

@ -42,11 +42,12 @@ chip soc/intel/alderlake
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoPci,
}"
register "serial_io_uart_mode" = "{
@ -60,7 +61,7 @@ chip soc/intel/alderlake
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.i2c[6] = {
.speed = I2C_SPEED_FAST,
},
}"
@ -119,7 +120,7 @@ chip soc/intel/alderlake
}"
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c6 on end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""