The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:
1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
compression to save flash space.
Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).
BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.
Normal Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Recovery Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
On Faegan the FSP supports RAS. Allow the user to configure
RAS features and pass them to the FSP using UPDs.
Change-Id: Ia7091d216a446d56632e64f9bba0e2a166410139
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In scenarios where the system is booting with a critical or low battery,
lowering the initial CPU frequency helps reduce the instantaneous power
draw, ensuring the battery can sustain the boot process while fast
charging is being enabled.
Changes:
- clock.h: Replace 806MHz (0x2A) with 710.4MHz (0x25) based on 19.2MHz
XO.
- mainboard.c: Update handle_low_power_charging_boot() to use the
new L-VAL and update the debug log accordingly.
BUG=b:436391478
Change-Id: Ida30824e344a4613c797083711c3f6ee31f9694d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Add clock_disable() (clear CBCR EN and poll CLK_OFF).
Add CBCR helper APIs and common bit definitions for HW_CTL,
FORCE_MEM_CORE_ON, IGNORE_RPMH_CLK_DIS and IGNORE_PMU_CLK_DIS.
BUG=None
TEST=Built and booted image.serial.bin on Bluey
Change-Id: I253414d01ec97aee45df1af0ed8cd06367351ef8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91546
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Boost the initial CPU frequency from 1.36GHz to ~3.0GHz (2995.2 MHz)
during the boot phase to reduce the execution time of ramstage
and subsequent payload loading.
Changes:
- clock.h: Add L_VAL_2995P2MHz (0x9C) based on a 19.2MHz XO.
- clock.c: Update speed_up_boot_cpu() to use the 3.0GHz PLL
multiplier for the APSS NCC0 clock.
This change helps in further optimizing the boot timeline,
leveraging the higher clock speed for faster initialization.
BUG=b:449871690
TEST=Able to save ~50ms of the boot time (mostly during Qclib).
Change-Id: I459001717298b10201c3b3c8bf6b0c20097ae830
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91818
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
On Qualcomm SoCs, the initial TTB is often placed in IMEM. During
ROMSTAGE, once DRAM is initialized and stable, the tables should be
moved to DRAM to ensure they remain accessible if IMEM is reclaimed
by other hardware blocks (like the ADSP).
Trigger mmu_relocate_ttb() at the end of the post-DRAM MMU
configuration flow.
BUG=b:436391478
TEST=Verify TTB moves to DRAM on Google/Quartz.
Debug logs:
```
[INFO ] Relocating TTB: 0x14842000 -> 0x80010000 (offset 0x6b7ce000)
[INFO ] TTB relocation is complete.
```
Change-Id: I123385e6cdd319c5ad4d3e7b266c506e7d2d5530
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91565
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Before trying to use the SPI flash controller in ramstage or SMM check
if the bus can be claimed. If ROM Armor is enabled abort claiming the
bus. Sanity check as the caller must use PSP mailbox interface when
ROM Armor is enabled.
This commit introduces SOC_AMD_COMMON_BLOCK_PSP_ROM_ARMOR3, that will
be used in the following commits to active ROM Armor support.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Id93747df92bfca46c15a1438c2804c0c574c9f99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a function to return ROM Armor state from HSTI bits.
As soon as ROM Armor is enforced never check HSTI bits again
as it cannot be deactivated without a reboot.
TEST=Function returns 0 before running command
MBOX_BIOS_CMD_ARMOR_ENTER_SMM_MODE and returns 1 after
sending it to PSP.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ic9cf99b7f2461aa85fbd76998da5d035bf9e5ae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CPU Control Processor (CPUCP) requires a dedicated memory region
for firmware loading. Previously, accessing this region without
explicit MMU configuration could lead to suboptimal performance
during the transfer.
```
CPUCP Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000001000 0x000000001cb00000 0x000000001cb00000
0x0000000000021d90 0x000000000002a630 RWE 0x1000
LOAD 0x0000000000023000 0x000000001cb2b000 0x000000001cb2b000
0x000000000000b570 0x000000000000b570 RW 0x1000
LOAD 0x000000000002f000 0x000000001cb3e000 0x000000001cb3e000
0x0000000000000890 0x0000000000000890 RW 0x1000
LOAD 0x0000000000000000 0x000000001cb3f000 0x000000001cb3f000
0x0000000000000000 0x0000000000001000 RW 0x1000
```
Key changes:
- symbols_common.h: Declare the 'cpucp' region.
- memlayout.ld: Define the CPUCP region at 0x1CB00000 (size 256K)
to align with SoC address maps.
- cpucp_load_reset.c: Map the CPUCP region as CACHED_RAM using
mmu_config_range() before loading the firmware.
- Flush and remap back the CPUCP range to device memory.
By ensuring the region is cached during the load and reset phase,
the firmware handoff is optimized, saving approximately 20ms of
overall boot time.
BUG=b:449871690
TEST=Able to save 20ms of the boot time.
Change-Id: I769f2cb7436ebfcc07eb2748b524066281a60a6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The CPUCP (CPU Control Processor) firmware for X1P42100 is being
loaded as a payload. Compressing this file in CBFS can lead to
loading delays with the early-stage.
Set the compression type to 'none' to ensure the ELF is stored
uncompressed.
BUG=b:449871690
TEST=Able to optimize boot time (tested on google/quartz) by ~200ms.
w/o this patch:
```
fallback/cpucp 0xc7500 simple elf 149498 none
```
w/ this patch:
```
fallback/cpucp 0xc7500 simple elf 496196 none
```
Change-Id: I77418ac05ad950943a538ad1c2976d5cdfe41324
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set defaults for VGA_BIOS_FILE and VGA_BIOS_ID.
TEST=Pre OS graphics init works on AMD/jaguar.
Change-Id: I3bf0e81b0de87abe4a03be8e10274936cf29e628
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Introduce `spmi_read8_safe` to handle transient SPMI bus errors that
can occur during early power sequencing. This helper implements a
retry mechanism (up to 6 attempts) with a 50ms delay between reads.
Providing a "safe" read wrapper prevents the system from misinterpreting
transient arbiter errors (ERROR_SPMI_READ_FAILED) as valid zero data,
which is critical for preventing premature power-offs when reading
input current .
BUG=b:436391478
BRANCH=none
TEST=Verified that SPMI read failures in the charging applet now
trigger the retry loop and successfully recover on Bluey.
Change-Id: Id1b770d2cd91ccb069933bd9b023b867a7507009
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To support this early hardware initiation, add pcie_common.c and
soc-specific pcie.c to the romstage build when
SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT and PCI Kconfigs are enabled.
This allows the SoC to kick off link training in romstage
and verify the link status later in ramstage.
BUG=b:449871690
TEST=Able to build and boot google/quenbih.
Change-Id: I6f81b88b36f51b55cb47846f9e81d0be8f987825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT to allow the PCIe
link training to proceed without blocking the boot flow.
Refactor qcom_setup_pcie_host into two logical phases:
1. Initiate: Power on endpoints and trigger LTSSM (Romstage).
2. Verify: Wait for link-up status (Ramstage).
When the async Kconfig is enabled, the initiation happens in
romstage, but the blocking 'wait_link_up' call is deferred to
ramstage. This allows other SoC and mainboard initializations to
run in between the hardware link training, reducing overall boot time.
BUG=b:449871690
TEST=Verified PCIe link still enumerates correctly on Bluey with
asynchronous init enabled.
Change-Id: Idf368731325b5efcf4db0d1912a8c75417ef11ab
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91723
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expand CBFS_MCACHE from 16K to 22K to provide more space for
metadata caching. To accommodate this, shift FMAP_CACHE from
0x14860400 to 0x14861800.
Updated the memory map diagram in memlayout.ld to reflect the
new base address for the FMAP_CACHE region.
TEST=No CBFS related error seen while booting google/quartz.
w/o patch:
```
[ERROR] CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
```
Change-Id: Ic3268c72a4755bd15c6811688eb330c7d753c5ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91698
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drain pending SPI sync SMIs before dropping write protect for SMMSTORE and once more after the command runs. This keeps a stale sync status from leaking into the next request.
Change-Id: I7ba21719a6dafa926b0d5986a253da9cff52575a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Provide the SoC-specific hardware definitions for the x1p42100 TSENS
subsystem. This includes the register base addresses for the four
TSENS controllers and the complete mapping of sensor IDs to thermal
zones (including AOSS, CPU, GPU, and NSP).
Each zone is assigned a specific thermal threshold to allow for
emergency shutdown triggers.
TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
Change-Id: Iffdd0589a3c5318b9754101d7cea40462435de5b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91610
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a generic driver for the Qualcomm Temperature Sensor (TSENS)
V2 hardware block. This driver provides the infrastructure to read
temperature data from hardware status registers and monitor them
against software-defined thresholds.
The driver sign-extends the 12-bit raw temperature values and scales
the output to millidegrees Celsius for accurate monitoring.
TEST=Verify all x1p42100 thermal zones are readable on Google/Quartz.
Change-Id: I826df3f86edc30ac57d84f672b487a8b9b51728a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91609
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the required definition for the 806 MHz CPU clock (L_VAL_806MHz).
Update pll_init_and_set by removing the static qualifier so it can be
invoked from the mainboard code.
Test: Built image.serial.bin and verified successful boot on X1P42100.
Change-Id: I8871f6cd64cb386c1042ce42feec4c623e9804e9
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Glinda is an alias for Strix. This only changes the SoC name in
amdfwtool; SoC folder will be renamed later once all remaining patches
have been upstreamed, since renaming the SoC folder right now, would
just make the upstreaming more difficult.
Change-Id: I10cb9c4a97dd2689fe02329262772b05d24a5896
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Drop send_psp_command_smm() and let the generic send_psp_command()
method handle SMM as special case. This allows to use the same
method in regular code and SMM.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I5dad79e80b97e9d4dfbcd0d84d49eb23ea3f83cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91702
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove WCL_ID_2 through WCL_ID_5 entries from the power mapping table
supports a single SKU configuration.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots
Change-Id: I95a8069c9b637c35936e6c0e5de257f7acbd8463
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91448
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CPHY mode, mtk_dsi_cphy_vdo_timing previously packed multiple values
into hfp_byte:
- Bits [7:0]: actual HFP byte count
- Bits [30:16]: hs_vb_ps_wc
- Bit 31: HFP_HS_EN flag
The previous error check treated the entire compound value as the HFP
byte count, resulting in false error messages like:
"Calculated hfp_byte -1850408952 and hbp_byte 4 are too small"
This patch refactors mtk_dsi_cphy_vdo_timing to return hfp_byte and
the upper bits (hfp_wc_upper) separately:
- hfp_byte now consistently represents the actual HFP byte count for
both CPHY and DPHY modes
- hfp_wc_upper contains hs_vb_ps_wc and HFP_HS_EN for CPHY (0 for DPHY)
- The values are combined when writing to dsi_hfp_wc register
This approach:
- Eliminates the need for mask operations in the caller
- Simplifies hfp/hbp validation and adjustment logic
- Makes hfp_byte semantically consistent across CPHY/DPHY
BUG=b:489932059
TEST=Boot and verify display output on MT8189 CPHY panel
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.com>
Change-Id: I46229c35f978a88276f4ae2a4582b2ea4164c1db
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91683
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
ADL programs this but MTL and PTL do not, so add it to the latter two
for consistency.
Change-Id: I8c982fcc810b3783cba4c66754df2b555bce6dfc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90878
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The PCIE_RP_BUILT_IN flag test is used only as a boolean condition, so
the double-negation is unnecessary. Also fix the comment grammar.
Change-Id: I5e1ff5848d9cedb2385892c795297719ccc1d5cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Switch Intel common block smihandler to use the generic x86
smm_save_state_ops instead of its own custom struct. Replace
find_save_state() and get_io_misc_info with apmc_node; use
node-based get_reg/set_reg functions. Alias em64t100_ops and
em64t101_ops for cpu/x86 save_state.c consumers.
TEST=tested with rest of patch train
Change-Id: Ie64478ccfdc0a0bda4354641aba06705e2c8c70d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
dsi-phy1 and dsi-phy2 are currently controlled using hardware voting,
however there is a low probability of power-off failure during the boot
process. Since dsi-phy1 and dsi-phy2 are not shared with different XPUs,
there is no need to control them using hardware voting. Change the
control method of dsi-phy1 and dsi-phy2 from hardware voting to software
control to fix the power-off failure issue.
BUG=b:477096462
TEST=Build Pass, Bootup OK and Suspend/Resume OK
Change-Id: I33ebbac0dd6d0d0d352697c14de9ecef28ba08cb
Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On Skylake mainboards, enablement of the Source Clock of a PCIe Root
Port is currently dependent on enablement of CLKREQ# in the devicetree.
However it may be desirable to disable CLKREQ# but still keep the Source
Clock enabled. Specifically, that's the recommended workaround for
erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from
ASPM L1 state:
"disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock
active during L1"
https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf
Therefore, key Source Clock enablement off of Root Port enablement in
the devicetree, rather than CLKREQ# enablement. A subsequent commit
takes advantage of this to implement the workaround on Google Pixelbook
Eve mainboards.
Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Expose API to return the microcode update block address. It will be
used to provide a pointer to microcode update to the OpenSIL.
Change-Id: I1a5a89a5ff2ed29621e856cf274434803005aff8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89108
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP for Arrow Lake supports Meteor Lake, so re-point coreboot
at that, as it's, simply, newer and better.
Change-Id: I524dc7c0632c9f38b178ad95563128b56f94f983
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two functions for disabling/enabling PCIe clocks to devices
connected to root ports. These functions are used during device power
sequencing at boot to ensure clocks are not driven to devices when
their power is off. This prevents potential issues with PCIe link
training and ensures proper power-on sequencing for connected devices.
BUG=none
TEST=Build and boot Panther Lake platform. Verify PCIe devices enumerate
correctly and clock management functions properly during power sequences
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I63f8e331b6ab18172fa32ff5c1539c71823aa247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91550
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel uses TPS65130RGER as the bias IC, with supply set to ±5.9V.
Configure TPS65130RGER initialization and power-on sequence according
to the tps65130.pdf.
The tps65132s driver is no longer used on this platform and remove it
from the build.
[INFO ] mtk_display_init: 'BOE NS130069' 3504x2190@120Hz bpp 4
BUG=b:463911061
TEST=Check display initialization log and display are normal
BRANCH=none
Change-Id: Idfc19597c4357adb818ca008f93bac2e7ebe3edb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91424
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure power state thresholds (PS1, PS2, PS3) according to the
platform design specification. These thresholds define current limits
at which the voltage regulator domains transition between different
power states for optimal power management.
Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ] (MAILBOX) PS1Threshold = 80 (1/4 Amp)
[SPEW ] (MAILBOX) PS2Threshold = 20 (1/4 Amp)
[SPEW ] (MAILBOX) PS3Threshold = 4 (1/4 Amp)
Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 835b63980d, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging.
BUG=b:490040385
Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This reverts commit 42210fdb28, which was causing the
ocelot DDR5 RVP to not boot. Reverting until further debugging.
BUG=b:490040385
Change-Id: I5185a036ccbd6cca19eb1a3fd762686ed03919e8
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The eDP AUX controller currently sets the NO_SEND_STOP flag for all
I2C-over-AUX transactions. This prevents the controller from issuing
an I2C STOP condition, which is required for proper completion of
multi-block (extended) EDID reads.
Update edp_msg_fifo_tx() to only set the EDP_AUX_TRANS_CTRL_NO_SEND_STOP
flag when the DP_AUX_I2C_MOT (Middle-of-Transaction) bit is set in the
request. This allows the I2C transaction to correctly finalize with a
STOP condition when MOT is not present, enabling successful reads of
EDID extension blocks.
BUG=none
TEST=Verify extended EDID is correctly read on Google/Quartz.
Change-Id: I4b637a750ef16148895332abfd9ca202b5a35408
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.
For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.
Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.
Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set IA voltage regulator to use IRMS mode with 28 second time window
for more accurate thermal design current measurement.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with the following
VR parameter
[SPEW ] TdcMode[0]:0x1
[SPEW ] TdcMode[1]:0x0
[SPEW ] TdcMode[2]:0x0
[SPEW ] TdcMode[3]:0x0
[SPEW ] TdcTimeWindow[0]:0x6D60
[SPEW ] TdcTimeWindow[1]:0x0
[SPEW ] TdcTimeWindow[2]:0x0
[SPEW ] TdcTimeWindow[3]:0x0
Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce mtk_mipi_panel_poweroff() in common display layer and
mtk_dsi_panel_poweroff() in DSI driver. The DSI mode flags are
saved during init and reused for the power-off command path.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: Ic684822bc5f20d3e2f5ce3d44035c902a2b44184
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91432
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The commit 7072f42c08f7 ("soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE
from SRAM to SRAM_L2C") move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
causes elog_handle_watchdog_tombstone (BS_POST_DEVICE, BS_ON_ENTRY) to
be invoked after mtk_mmu_disable_l2c_sram. As a result, the watchdog
event magic value in WATCHDOG_TOMBSTONE is cleared before it can be
processed, which is incorrect behavior.
So we refactor the mtk_mmu_disable_l2c_sram to be called as a boot state
entry (BS_POST_DEVICE, BS_ON_EXIT) instead of directly from soc_init.
This ensures that mtk_mmu_disable_l2c_sram will be executed after
elog_handle_watchdog_tombstone.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout (triggered via echo > /dev/watchdog)
TEST=cbmem logs preserved on WDT timeout
Change-Id: I69ef567ab73f2f7006bb249cb577f377d4720909
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout
Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/pantherlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Meteor Lake, making
it an ideal candidate for consolidation.
Change-Id: I749eea246fdc7ab89848ed4160c61666e8944095
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/meteorlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Panther Lake, making
it an ideal candidate for consolidation.
Change-Id: Id0c3bde3b721b7a3e497711cfc6dd21efbfda4c5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
