Sowmya Aralguppe 0be9f20be4 soc/intel/pantherlake: Add icc_max settings for WCL SKU ... Add icc maximum configuration to include all voltage regulator domains for WCL_SKU_1 Ref=830097_WCL_PDG_SchChk_Rev1p5 BUG=b:None TEST=Build ocelot and verify that the system boots with following VR parameter [SPEW ] (MAILBOX) IccMax = 200 (1/4 A) [SPEW ] Override IccMax[1] = 144 [SPEW ] (MAILBOX) IccMax = 144 (1/4 A) [SPEW ] Override IccMax[2] = 140 [SPEW ] (MAILBOX) IccMax = 140 (1/4 A) [SPEW ] Override IccMax[3] = 112 [SPEW ] (MAILBOX) IccMax = 112 (1/4 A) Change-Id: Ic1a17834a3164c7d0747d1aa0cde01de637535a3 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91453 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2026-03-10 12:22:48 +00:00
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amd	soc/amd/turin_poc: Add SPI TPM SoC-specific initialization	2026-03-02 14:38:58 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/pantherlake: Add icc_max settings for WCL SKU	2026-03-10 12:22:48 +00:00
mediatek	soc/mediatek: Add mtk_mipi_panel_poweroff()	2026-03-05 15:30:16 +00:00
nvidia	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
qualcomm	soc/qc/common: Configure framebuffer as uncacheable	2026-03-10 12:22:35 +00:00
rockchip	treewide: Move mipi_panel_parse_commands() to commonlib	2026-01-14 09:38:36 +00:00
samsung
sifive
ti
ucb/riscv
xilinx