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soc/intel/pantherlake: Add power state thresholds for WCL

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Configure power state thresholds (PS1, PS2, PS3) according to the
platform design specification. These thresholds define current limits
at which the voltage regulator domains transition between different
power states for optimal power management.

Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ]  (MAILBOX) PS1Threshold         = 80 (1/4 Amp)
[SPEW ]  (MAILBOX) PS2Threshold         = 20 (1/4 Amp)
[SPEW ]  (MAILBOX) PS3Threshold         = 4 (1/4 Amp)

Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sowmya Aralguppe 2026-02-27 14:40:04 +05:30 • committed by Matt DeVillier
commit eb5bdf06b9
1 changed files with 17 additions and 0 deletions
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17
src/soc/intel/pantherlake/chipset_wcl.cb
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@ -14,6 +14,23 @@ chip soc/intel/pantherlake
register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
# Set the power state thresholds according to document 830097
# Wildcat Lake Platform - Design Guide - Rev 1.5
register "ps1_threshold" = "{
[VR_DOMAIN_IA] = 20 * 4,
[VR_DOMAIN_GT] = 20 * 4,
[VR_DOMAIN_SA] = 20 * 4
}"
register "ps2_threshold" = "{
[VR_DOMAIN_IA] = 5 * 4,
[VR_DOMAIN_GT] = 5 * 4,
[VR_DOMAIN_SA] = 5 * 4
}"
register "ps3_threshold" = "{
[VR_DOMAIN_IA] = 1 * 4,
[VR_DOMAIN_GT] = 1 * 4,
[VR_DOMAIN_SA] = 1 * 4
}"
# Reduce the size of BasicMemoryTests to speed up the boot time.
register "lower_basic_mem_test_size" = "true"