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soc/intel/{mtl,ptl}/fsp_params: Program PcieRpSlotImplemented

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ADL programs this but MTL and PTL do not, so add it to the latter two
for consistency.

Change-Id: I8c982fcc810b3783cba4c66754df2b555bce6dfc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90878
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2026-01-23 11:28:14 -06:00 • committed by Sean Rhodes
commit b03b42285e
2 changed files with 6 additions and 0 deletions
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3
src/soc/intel/meteorlake/fsp_params.c
View file

@ -641,6 +641,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
if (rp_cfg->flags & PCIE_RP_BUILT_IN)
s_cfg->PcieRpSlotImplemented[i] = false;
s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
configure_pch_rp_power_management(s_cfg, rp_cfg, i);
}

3
src/soc/intel/pantherlake/fsp_params.c
View file

@ -601,6 +601,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpHotPlug[i] =
!!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
if (rp_cfg->flags & PCIE_RP_BUILT_IN)
s_cfg->PcieRpSlotImplemented[i] = false;
s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
configure_pch_rp_power_management(s_cfg, rp_cfg, i);
}