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soc/intel/pantherlake: Add icc_max settings for WCL SKU

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Add icc maximum configuration to include all voltage regulator domains
for WCL_SKU_1

Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ]  (MAILBOX) IccMax    = 200 (1/4 A)
[SPEW ]   Override IccMax[1] = 144
[SPEW ]  (MAILBOX) IccMax    = 144 (1/4 A)
[SPEW ]   Override IccMax[2] = 140
[SPEW ]  (MAILBOX) IccMax    = 140 (1/4 A)
[SPEW ]   Override IccMax[3] = 112
[SPEW ]  (MAILBOX) IccMax    = 112 (1/4 A)

Change-Id: Ic1a17834a3164c7d0747d1aa0cde01de637535a3
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91453
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya Aralguppe 2026-02-27 14:18:53 +05:30 • committed by Matt DeVillier
commit 0be9f20be4
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/pantherlake/chipset_wcl.cb
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@ -9,7 +9,10 @@ chip soc/intel/pantherlake
}"
register "icc_max[WCL_SKU_1]" = "{
[VR_DOMAIN_IA] = 50 * 4,
[VR_DOMAIN_GT] = 36 * 4,
[VR_DOMAIN_SA] = 35 * 4,
[VR_DOMAIN_ATOM] = 28 * 4
}"
register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"