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soc/qualcomm/x1p42100: Increase CBFS_MCACHE size to 22K

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Expand CBFS_MCACHE from 16K to 22K to provide more space for
metadata caching. To accommodate this, shift FMAP_CACHE from
0x14860400 to 0x14861800.

Updated the memory map diagram in memlayout.ld to reflect the
new base address for the FMAP_CACHE region.

TEST=No CBFS related error seen while booting google/quartz.

w/o patch:

```
[ERROR]  CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
```

Change-Id: Ic3268c72a4755bd15c6811688eb330c7d753c5ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91698
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2026-03-17 11:53:19 +05:30
commit 8a90e46346
1 changed files with 3 additions and 3 deletions
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6
src/soc/qualcomm/x1p42100/memlayout.ld
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@ -132,7 +132,7 @@
* | ... Usable memory ... | |
* 0x14860C00 +----------------------------------------------------------+ |
* | FMAP_CACHE | |
* 0x14860000 +----------------------------------------------------------+ BSRAM
* 0x14861800 +----------------------------------------------------------+ BSRAM
* | CBFS_MCACHE | |
* 0x1485C000 +----------------------------------------------------------+ |
* | qclib_serial_log | |
@ -217,8 +217,8 @@ SECTIONS
VBOOT2_WORK(0x14854000, 12K)
PRERAM_DMA_COHERENT(0x14858000, 8K)
REGION(qclib_serial_log, 0x1485B000, 4K, 4K)
CBFS_MCACHE(0x1485C000,16K)
FMAP_CACHE(0x14860400, 2K)
CBFS_MCACHE(0x1485C000,22K)
FMAP_CACHE(0x14861800, 2K)
REGION(dcb, 0x14862000, 56K, 4K)
REGION(dtb, 0x14870000, 32K, 4K)
REGION(ddr_training, 0x14878000, 64K, 4K)