soc/intel/ptl: Add ISCLK for controlling PCIe clock source

Add two functions for disabling/enabling PCIe clocks to devices
connected to root ports. These functions are used during device power
sequencing at boot to ensure clocks are not driven to devices when
their power is off. This prevents potential issues with PCIe link
training and ensures proper power-on sequencing for connected devices.

BUG=none
TEST=Build and boot Panther Lake platform. Verify PCIe devices enumerate
correctly and clock management functions properly during power sequences

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I63f8e331b6ab18172fa32ff5c1539c71823aa247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91550
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/pantherlake/Makefile.mk

@@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/intel/turbo
 
 # all (bootblock, verstage, romstage, postcar, ramstage)
 all-y += gpio.c
+all-y += isclk.c
 
 bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pcd.c

src/soc/intel/pantherlake/include/soc/isclk.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_PANTHERLAKE_ISCLK_H_
+#define _SOC_PANTHERLAKE_ISCLK_H_
+
+#include <types.h>
+
+/* Disable PCIe clock source; clock_number: 0-based */
+void soc_disable_pcie_clock_out(size_t clock_number);
+
+/* Enable PCIe clock source; clock_number: 0-based */
+void soc_enable_pcie_clock_out(size_t clock_number);
+
+#endif /* _SOC_PANTHERLAKE_ISCLK_H_ */

src/soc/intel/pantherlake/isclk.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/isclk.h>
+#include <soc/pcr_ids.h>
+
+#define ISCLK_PCR_BIOS_BUFFEN_H 0x8080
+
+/* Disable PCIe clock source; clock_number: 0-based */
+void soc_disable_pcie_clock_out(size_t clock_number)
+{
+	pcr_rmw32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, ~BIT(clock_number), 0);
+}
+
+/* Enable PCIe clock source; clock_number: 0-based */
+void soc_enable_pcie_clock_out(size_t clock_number)
+{
+	pcr_or32(PID_ISCLK, ISCLK_PCR_BIOS_BUFFEN_H, BIT(clock_number));
+}