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soc/qualcomm/x1p42100: Allow asynchronous PCIe initialization

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To support this early hardware initiation, add pcie_common.c and
soc-specific pcie.c to the romstage build when
SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT and PCI Kconfigs are enabled.

This allows the SoC to kick off link training in romstage
and verify the link status later in ramstage.

BUG=b:449871690
TEST=Able to build and boot google/quenbih.

Change-Id: I6f81b88b36f51b55cb47846f9e81d0be8f987825
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2026-03-18 13:58:06 +05:30
commit f56a936c54
1 changed files with 4 additions and 0 deletions
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4
src/soc/qualcomm/x1p42100/Makefile.mk
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@ -38,6 +38,10 @@ romstage-y += ../common/aop_load_reset.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
romstage-y += ../common/spmi.c
romstage-y += pmic.c
ifeq ($(CONFIG_SOC_QUALCOMM_PCIE_ASYNCHRONOUS_INIT),y)
romstage-$(CONFIG_PCI) += ../common/pcie_common.c
romstage-$(CONFIG_PCI) += pcie.c
endif
################################################################################
ramstage-y += soc.c