faf12bcacd
On Skylake mainboards, enablement of the Source Clock of a PCIe Root
Port is currently dependent on enablement of CLKREQ# in the devicetree.
However it may be desirable to disable CLKREQ# but still keep the Source
Clock enabled. Specifically, that's the recommended workaround for
erratum 47 of Sunrise Point-LP PCHs, which concerns exit instability from
ASPM L1 state:
"disable the associated PCH SRCCLKREQ# signal to keep the PCIe clock
active during L1"
https://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/100-series-chipset-spec-update.pdf
Therefore, key Source Clock enablement off of Root Port enablement in
the devicetree, rather than CLKREQ# enablement. A subsequent commit
takes advantage of this to implement the workaround on Google Pixelbook
Eve mainboards.
Change-Id: I9b69357c59bad3392da85e0629a9d368524daffd
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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| example/min86 | ||
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| intel | ||
| mediatek | ||
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| qualcomm | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| ti | ||
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