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Revert "soc/intel/pantherlake: Fill in SPD data on both channels of DDR5 memory"

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This reverts commit 42210fdb28, which was causing the
ocelot DDR5 RVP to not boot. Reverting until further debugging.

BUG=b:490040385

Change-Id: I5185a036ccbd6cca19eb1a3fd762686ed03919e8
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Avi Uday 2026-03-06 10:34:10 +05:30 • committed by Matt DeVillier
commit ea58a467f1
1 changed files with 13 additions and 18 deletions
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31
src/soc/intel/pantherlake/meminit.c
View file

@ -70,8 +70,7 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
},
};
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data,
bool expand_channels)
static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
{
uint64_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
@ -104,19 +103,7 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
uint64_t *spd_ptr = spd_upds[ch][dimm];
/*
* In DDR5 systems, since each DIMM has 2 channels,
* we need to copy the SPD data such that:
* Channel 0 data is used by channel 0 and 1
* Channel 2 data is used by channel 2 and 3
* Channel 4 data is used by channel 4 and 5
* Channel 6 data is used by channel 6 and 7
*/
if (expand_channels)
*spd_ptr = data->spd[ch & ~1][dimm];
else
*spd_ptr = data->spd[ch][dimm];
*spd_ptr = data->spd[ch][dimm];
if (*spd_ptr)
enable_channel = 1;
}
@ -197,7 +184,6 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
{
struct mem_channel_data data;
bool dq_dqs_auto_detect = false;
bool expand_channels = false;
FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
mem_cfg->ECT = mb_cfg->ect;
@ -209,7 +195,16 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__);
meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
dq_dqs_auto_detect = true;
expand_channels = true;
/*
* TODO: Drop this workaround once SMBus driver in coreboot is
* updated to support DDR5 EEPROM reading.
*/
if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
return;
}
break;
case MEM_TYPE_LP5X:
meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config);
@ -223,7 +218,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info,
half_populated, &data);
mem_init_spd_upds(mem_cfg, &data, expand_channels);
mem_init_spd_upds(mem_cfg, &data);
mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect);
}