soc/qualcomm/x1p42100: Add 806 MHz CPU clock definition

Add the required definition for the 806 MHz CPU clock (L_VAL_806MHz).
Update pll_init_and_set by removing the static qualifier so it can be
invoked from the mainboard code.

Test: Built image.serial.bin and verified successful boot on X1P42100.

Change-Id: I8871f6cd64cb386c1042ce42feec4c623e9804e9
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/qualcomm/x1p42100/clock.c

@@ -612,7 +612,7 @@ enum cb_err usb_clock_configure_mux(enum clk_pipe_usb clk_type, u32 src_type)
 	return CB_SUCCESS;
 }
 
-static enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
+enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val)
 {
 	int ret;
 	struct alpha_pll_reg_val_config ncc0_pll_cfg = {0};

src/soc/qualcomm/x1p42100/include/soc/clock.h

@@ -20,6 +20,7 @@
 
 /* CPU PLL*/
 #define L_VAL_1363P2MHz		0x47
+#define L_VAL_806MHz		0x2A
 
 /* DISP PLL */
 #define L_VAL_1725MHz		0x59
@@ -892,6 +893,7 @@ enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
 enum cb_err disp_pll_init_and_set(struct x1p42100_disp_pll_clock *disp_pll,
 		u32 l_val, u32 alpha_val);
 enum cb_err lpass_init(void);
+enum cb_err pll_init_and_set(struct x1p42100_ncc0_clock *ncc0, u32 l_val);
 
 void clock_configure_dfsr_table_x1p42100(int qup, struct clock_freq_config *clk_cfg,
 		uint32_t num_perfs);