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soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C

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The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.

The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).

On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.

Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.

BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout

Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jarried Lin 2026-03-04 12:52:10 +08:00 • committed by Yidi Lin
commit 510e43d8bd
1 changed files with 6 additions and 3 deletions
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9
src/soc/mediatek/mt8196/include/soc/memlayout.ld
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@ -13,13 +13,15 @@
SECTIONS
{
/* MT8196 has 256KB SRAM. */
/* MT8196 has 256KB SRAM. Per HW design, on SoC reset via GPIO
* AP_SYSRST_ODL (SYSRSTB), SRAM will be powered down. That means
* SRAM data will be lost across SoC resets.
*/
SRAM_START(0x00100000)
/* Regions that need to stay in SRAM. */
TTB(0x00100000, 28K)
DMA_COHERENT(0x00107000, 4K)
STACK(0x00108000, 15K)
WATCHDOG_TOMBSTONE(0x0010bc00, 4)
EARLY_INIT(0x0010bc10, 128)
/* EMPTY(0x0010bc90, 29K - 144) */
/*
@ -56,7 +58,8 @@ SECTIONS
#endif
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K)
PRERAM_CBFS_CACHE(0x020DA000, 48K)
PRERAM_CBMEM_CONSOLE(0x020E6000, 340K)
PRERAM_CBMEM_CONSOLE(0x020E6000, 339K)
WATCHDOG_TOMBSTONE(0x0213AC00, 4)
FSP_ROMSTAGE_INIT_CODE(0x02140000, 64K)
SRAM_L2C_END(0x02200000)