soc/qualcomm/common: add CBCR disable and config helpers
Add clock_disable() (clear CBCR EN and poll CLK_OFF). Add CBCR helper APIs and common bit definitions for HW_CTL, FORCE_MEM_CORE_ON, IGNORE_RPMH_CLK_DIS and IGNORE_PMU_CLK_DIS. BUG=None TEST=Built and booted image.serial.bin on Bluey Change-Id: I253414d01ec97aee45df1af0ed8cd06367351ef8 Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91546 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Hari L
Subrata Banik
parent
2e3e690023
commit
a58f752d0f
2 changed files with 97 additions and 9 deletions
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@ -17,7 +17,7 @@ static bool clock_is_off(u32 *cbcr_addr)
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enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
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uint32_t vote_bit)
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{
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int count = 100;
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int count = CLK_POLL_COUNT;
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setbits32(vote_addr, BIT(vote_bit));
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@ -34,7 +34,7 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
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enum cb_err clock_enable(void *cbcr_addr)
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{
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int count = 100;
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int count = CLK_POLL_COUNT;
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/* Set clock enable bit */
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setbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT));
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@ -50,6 +50,74 @@ enum cb_err clock_enable(void *cbcr_addr)
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return CB_ERR;
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}
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enum cb_err clock_disable(void *cbcr_addr)
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{
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int count = CLK_POLL_COUNT;
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if (!cbcr_addr)
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return CB_ERR;
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/* Clear clock enable bit */
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clrbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT));
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/* Ensure clock is disabled */
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while (count-- > 0) {
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if (clock_is_off(cbcr_addr))
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return CB_SUCCESS;
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udelay(1);
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}
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printk(BIOS_ERR, "Failed to disable clock, register val: 0x%x\n",
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read32(cbcr_addr));
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return CB_ERR;
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}
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void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable)
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{
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if (!cbcr_addr)
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return;
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if (enable)
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setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT));
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else
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clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT));
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}
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void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable)
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{
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if (!cbcr_addr)
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return;
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if (enable)
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setbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT));
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else
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clrbits32(cbcr_addr, BIT(CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT));
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}
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void clock_configure_hw_ctl(void *cbcr_addr, bool enable)
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{
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if (!cbcr_addr)
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return;
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/* Enable or disable hardware-controlled clock gating */
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if (enable)
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setbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT));
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else
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clrbits32(cbcr_addr, BIT(CLK_CTL_HW_CTL_SHFT));
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}
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void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable)
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{
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if (!cbcr_addr)
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return;
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/* Forces core-on signal to stay active during clk halt */
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if (enable)
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setbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT));
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else
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clrbits32(cbcr_addr, BIT(CLK_CTL_FORCE_MEM_CORE_ON_SHFT));
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}
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/* Clock Block Reset Operations */
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void clock_reset_bcr(void *bcr_addr, bool assert)
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{
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@ -77,7 +145,7 @@ enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr)
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clrbits32(gdscr_addr, BIT(GDSC_ENABLE_BIT));
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/* Ensure gdsc is enabled */
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if (!wait_us(100, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK)))
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if (!wait_us(CLK_WAIT_US_TIMEOUT, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK)))
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return CB_ERR;
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return CB_SUCCESS;
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@ -227,7 +295,7 @@ enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg,
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setbits32(cfg->reg_apcs_pll_br_en, BIT(br_enable));
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/* Wait for Lock Detection */
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if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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printk(BIOS_ERR, "PLL did not lock!\n");
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return CB_ERR;
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}
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@ -247,7 +315,7 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg)
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udelay(5);
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setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
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if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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printk(BIOS_ERR, "CPU PLL did not lock!\n");
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return CB_ERR;
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}
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@ -269,7 +337,7 @@ enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg)
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setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
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setbits32(cfg->reg_opmode, PLL_RUN_MODE);
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if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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printk(BIOS_ERR, "CPU PLL did not lock!\n");
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return CB_ERR;
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}
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@ -292,7 +360,7 @@ enum cb_err zondaole_pll_enable(struct alpha_pll_reg_val_config *cfg)
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setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
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setbits32(cfg->reg_opmode, PLL_RUN_MODE);
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if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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printk(BIOS_ERR, "CPU PLL did not lock!\n");
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return CB_ERR;
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}
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@ -312,7 +380,7 @@ enum cb_err lucidole_pll_enable(struct alpha_pll_reg_val_config *cfg)
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setbits32(cfg->reg_opmode, PLL_RUN_MODE);
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setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
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if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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if (!wait_us(CLK_WAIT_US_TIMEOUT, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
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printk(BIOS_ERR, "CPU PLL did not lock!\n");
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return CB_ERR;
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}
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@ -4,6 +4,8 @@
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#define __SOC_QUALCOMM_COMMON_CLOCK_H__
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#define QCOM_CLOCK_DIV(div) (2 * div - 1)
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#define CLK_POLL_COUNT 100
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#define CLK_WAIT_US_TIMEOUT 100
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/* Root Clock Generator */
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struct clock_rcg {
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@ -124,11 +126,19 @@ enum clk_ctl_cmd_rcgr {
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enum clk_ctl_cbcr {
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CLK_CTL_EN_SHFT = 0,
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CLK_CTL_HW_CTL_SHFT = 1,
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CLK_CTL_ARES_SHFT = 2,
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CLK_CTL_FORCE_MEM_CORE_ON_SHFT = 14,
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CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT = 20,
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CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT = 21,
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CLK_CTL_OFF_SHFT = 31,
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CLK_CTL_EN_BMSK = 0x1,
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CLK_CTL_HW_CTL_BMSK = 0x1 << CLK_CTL_HW_CTL_SHFT,
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CLK_CTL_ARES_BMSK = 0x1 << CLK_CTL_ARES_SHFT,
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CLK_CTL_OFF_BMSK = 0x80000000,
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CLK_CTL_FORCE_MEM_CORE_ON_BMSK = 0x1 << CLK_CTL_FORCE_MEM_CORE_ON_SHFT,
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CLK_CTL_IGNORE_RPMH_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_RPMH_CLK_DIS_SHFT,
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CLK_CTL_IGNORE_PMU_CLK_DIS_BMSK = 0x1 << CLK_CTL_IGNORE_PMU_CLK_DIS_SHFT,
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CLK_CTL_OFF_BMSK = 0x1 << CLK_CTL_OFF_SHFT,
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};
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enum clk_ctl_rcg_mnd {
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@ -155,6 +165,16 @@ enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr,
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enum cb_err clock_enable(void *cbcr_addr);
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enum cb_err clock_disable(void *cbcr_addr);
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void clock_configure_ignore_rpmh_clk_dis(void *cbcr_addr, bool enable);
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void clock_configure_ignore_pmu_clk_dis(void *cbcr_addr, bool enable);
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void clock_configure_hw_ctl(void *cbcr_addr, bool enable);
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void clock_configure_force_mem_core_on(void *cbcr_addr, bool enable);
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enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr);
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void clock_reset_bcr(void *bcr_addr, bool assert);
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