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soc/intel/alderlake/fsp_params: Drop !! in builtin root port check

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The PCIE_RP_BUILT_IN flag test is used only as a boolean condition, so
the double-negation is unnecessary. Also fix the comment grammar.

Change-Id: I5e1ff5848d9cedb2385892c795297719ccc1d5cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2026-03-17 12:38:39 -05:00 • committed by Sean Rhodes
commit e17cc395af
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/fsp_params.c
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@ -967,8 +967,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
/* PcieRpSlotImplemented default to 1 (slot implemented) in FSP; 0: built-in */
if (!!(rp_cfg->flags & PCIE_RP_BUILT_IN))
/* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */
if (rp_cfg->flags & PCIE_RP_BUILT_IN)
s_cfg->PcieRpSlotImplemented[i] = false;
s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
configure_pch_rp_power_management(s_cfg, rp_cfg, i);