soc/qualcomm/x1p42100: Define CPUCP region and map in MMU

The CPU Control Processor (CPUCP) requires a dedicated memory region
for firmware loading. Previously, accessing this region without
explicit MMU configuration could lead to suboptimal performance
during the transfer.

```
CPUCP Program Headers:
Type     Offset             VirtAddr           PhysAddr
         FileSiz            MemSiz              Flags  Align

LOAD     0x0000000000001000 0x000000001cb00000 0x000000001cb00000
         0x0000000000021d90 0x000000000002a630  RWE    0x1000
LOAD     0x0000000000023000 0x000000001cb2b000 0x000000001cb2b000
         0x000000000000b570 0x000000000000b570  RW     0x1000
LOAD     0x000000000002f000 0x000000001cb3e000 0x000000001cb3e000
         0x0000000000000890 0x0000000000000890  RW     0x1000
LOAD     0x0000000000000000 0x000000001cb3f000 0x000000001cb3f000
         0x0000000000000000 0x0000000000001000  RW     0x1000
```

Key changes:
- symbols_common.h: Declare the 'cpucp' region.
- memlayout.ld: Define the CPUCP region at 0x1CB00000 (size 256K)
  to align with SoC address maps.
- cpucp_load_reset.c: Map the CPUCP region as CACHED_RAM using
  mmu_config_range() before loading the firmware.
- Flush and remap back the CPUCP range to device memory.

By ensuring the region is cached during the load and reset phase,
the firmware handoff is optimized, saving approximately 20ms of
overall boot time.

BUG=b:449871690
TEST=Able to save 20ms of the boot time.

Change-Id: I769f2cb7436ebfcc07eb2748b524066281a60a6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>

src/soc/qualcomm/common/include/soc/symbols_common.h

@@ -31,6 +31,7 @@ DECLARE_REGION(dram_modem_extra)
 DECLARE_REGION(dram_wlan)
 DECLARE_REGION(dram_wpss)
 DECLARE_REGION(shrm)
+DECLARE_REGION(cpucp)
 DECLARE_REGION(dram_cpucp_dtbs)
 DECLARE_REGION(dram_cpucp)
 DECLARE_REGION(dram_modem)

src/soc/qualcomm/x1p42100/cpucp_load_reset.c

@@ -1,13 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/cache.h>
+#include <arch/mmu.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <soc/cpucp.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
+#include <soc/mmu_common.h>
+#include <soc/symbols_common.h>
+#include <symbols.h>
 
 void cpucp_fw_load_reset(void)
 {
+	/* map to cached region to force address to be 4 byte aligned */
+	mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), CACHED_RAM);
+
 	struct prog cpucp_dtbs_prog =
 		PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs");
 
@@ -22,6 +30,11 @@ void cpucp_fw_load_reset(void)
 	if (!selfload(&cpucp_fw_prog))
 		die("SOC image: CPUCP load failed");
 
+	/* flush cached region */
+	dcache_clean_by_mva(_cpucp, REGION_SIZE(cpucp));
+	/* remap back to device memory */
+	mmu_config_range((void *)_cpucp, REGION_SIZE(cpucp), DEV_MEM);
+
 	printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n");
 
 	write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0);

src/soc/qualcomm/x1p42100/memlayout.ld

@@ -98,6 +98,10 @@
  *               |                         shrm                             |    SHRM
  * 0x24040000    +----------------------------------------------------------+ <---------
  *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
+ * 0x1CB40000    +----------------------------------------------------------+ <---------
+ *               |                         CPUCP                            |
+ * 0x1CB00000    +----------------------------------------------------------+ <---------
+ *               |         ... (Memory not mapped: Unavailable) ...         | XXXXXXXXX
  * 0x14A80000    +----------------------------------------------------------+ <---------
  *               |                    auth_metadata                         |      ^
  * 0x14A7E000    +----------------------------------------------------------+      |
@@ -233,6 +237,8 @@ SECTIONS
 	REGION(auth_metadata, 0x14A7E000, 8K, 4K)
 	BSRAM_END(0x14A80000)
 
+	REGION(cpucp, 0x1CB00000, 256K , 4K)
+
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)