Revert "soc/intel/pantherlake: Fix DDR5 channel mapping"

This reverts commit 835b63980d, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging.

BUG=b:490040385

Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>

src/soc/intel/pantherlake/meminit.c

@@ -35,16 +35,18 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 		.num_phys_channels = DDR5_CHANNELS,
 		.phys_to_mrc_map = {
 			[0] = 0,
-			[1] = 4,
+			[1] = 1,
+			[2] = 4,
+			[3] = 5,
 		},
 		.md_phy_masks = {
 			/*
-			 * Only channel 0 is populated in case of half-populated
-			 * configuration.
+			 * Physical channels 0 and 1 are populated in case of
+			 * half-populated configurations.
 			 */
-			.half_channel = BIT(0),
-			/* In mixed topologies, either channel 0 or 1 can be memory-down. */
-			.mixed_topo = BIT(0) | BIT(1),
+			.half_channel = BIT(0) | BIT(1),
+			/* In mixed topology, channels 2 and 3 are always memory-down. */
+			.mixed_topo = BIT(2) | BIT(3),
 		},
 	},
 	[MEM_TYPE_LP5X] = {