soc/qualcomm/x1p42100: Add API to configure LPASS GPIO

Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.

For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.

Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.

Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Swathi Tamilselvan 2026-02-26 10:06:07 +05:30 committed by Subrata Banik
commit 1d8c536d79
2 changed files with 16 additions and 0 deletions

View file

@ -23,6 +23,20 @@ void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
write32(&regs->cfg, reg_val);
}
void gpio_configure_no_egpio(gpio_t gpio, uint32_t func, uint32_t pull,
uint32_t drive_str, uint32_t enable)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
uint32_t reg_val;
reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) |
((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
write32(&regs->cfg, reg_val);
}
void gpio_set(gpio_t gpio, int value)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;

View file

@ -99,6 +99,8 @@ struct tlmm_gpio {
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
uint32_t drive_str, uint32_t enable);
void gpio_configure_no_egpio(gpio_t gpio, uint32_t func, uint32_t pull,
uint32_t drive_str, uint32_t enable);
void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull);
int gpio_irq_status(gpio_t gpio);