Move LZ4 magic number definitions to public header file so that it can
be used in the payload. Also rename LEGACY_MAGICNUMBER to
LZ4_LEGACY_MAGICNUMBER for clarity when using from the payload.
BUG=None
TEST=Build Hylia BIOS image and boot to OS/UI.
Change-Id: Ief180105ec3fa7abf1013d0c5408aa96edde681b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable TCP0 alongside TCP1.
Test=build and boot adl/horizon, check there is video output over
USB-C.
Change-Id: I9db17fd3ed3e1eb0f6ea94320b595ce0d51f33e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91168
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the entries were indexed wrong, so fix them.
Change-Id: I76890a3c3b2b30d8123a81352346776a656e8f7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91167
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:480035819
TEST=Build successfully for kulnex. Verify WiFi 7 functionality on
moxie.
Change-Id: I46dfe87afe7356cbe48cf15dd87a58b55a528094
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91071
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the PCIe features can be programmed FSP-S must set non
public bits in the EnumInitPhaseAfterPciEnumeration callback.
Violating this rule causes system instabilities and reboot loops,
depending on the selected features and hardware plugged into slots.
Since FSP-S can handle all types of PCIe features disable all of
them in coreboot and let FSP set the bits at the right time.
TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing
system crashed.
Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select SOC_AMD_SUPPORTS_WARM_RESET on faegon only.
Glinda doesn't currently support warm resets.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Ic7a011827d16685bb3f2a13a576b7832a4929119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default CPU for birman_plus is STX1FP8 with a TDP of 28W.
Set SystemConfig to 2 to use the default IRM configuration
for 28W TDP CPUs and tweak slow PPT and fast PPT.
Change-Id: I555326228ad6a1dfa2f18c7fbd5a69b9b95b0f04
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently FSP modifies the AOAC bits of the FCH devices and
thus needs the current status passed via fch_rt_device_enable_map.
By default fch_rt_device_enable_map is 0, effectly disabling all FCH
devices, including the debug UART. This causes a hang at boot.
Fill fch_rt_device_enable_map in SoC code.
TEST=Can boot on amd/birman_plus again.
Change-Id: I00ef35ea6fe11939c4154940fef8cb902955fe27
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing logic prioritized the check for ENV_ROMSTAGE_OR_BEFORE
over the HAVE_EARLY_POWEROFF_SUPPORT configuration. This meant that
platforms with early poweroff support might still fall through to the
incorrect path depending on the boot phase.
Refactor the logic to:
1. Prioritize CONFIG(HAVE_EARLY_POWEROFF_SUPPORT) as the primary
mechanism for poweroff.
2. If early support is not available, check the environment stage:
- Perform standard pmc_control_poweroff() if after romstage.
- Halt with an emergency message if attempted too early in the
boot process without platform support.
This structure ensures that platform-specific early poweroff routines
are always preferred when configured.
TEST=Able to verify the AC host event is not getting cleared after
power-off.
Change-Id: Ieec8bcae5e1002d264db59cafe9236aaef6576e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Moves the variables to more appropriate locations to save some lines and
make it more readable. For x86 it now also adds the intermediate, but
since x86 doesn't define any regions (e.g. ramstage) to check against,
the intermediate is effectively skipped.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I28371ae3416040243f238271ba45238ceccfcf0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90816
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A Windows driver bug resulted in the max98357a-tdm topology being
identified as the correct one, when in fact the non-TDM version is
correct. Now that the bug has been fixed, correct the speaker
topology. Linux was unaffacted as it uses a different mapping
method.
TEST=build/boot Win11 on RPL Taeko, verify audio functional out
of both left/right speakers and mixer functions properly.
Change-Id: I2f9cc7353540cd8722beada656a8c2a8b1ba8669
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91144
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When SMBIOS_TYPE4_SOCKETED_CPU is selected advertise upgrade
support in SMBIOS Type4 table.
Change-Id: I877c72592277690cdfa9ac6805697494c0e87b4e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91146
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the Sandybridge Lenovo devices are spending 25msec waiting
for ME to signal if RAM has been replaced. At the same time the RFID
I2C EEPROM needs to be locked, taking about 26msec.
By moving the locking to romstage the time spent waiting for ME can
be used to do something useful and thus reduce boot time.
TEST=On Lenovo X220 it boots 24msec faster.
Change-Id: Idd1f02a20dab6e422d55e3cf01d7b4a168792272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Create the kulnex variant of the kuldax project by
copying the files to a new directory named for the variant.
BUG=b:480035819
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULNEX
Change-Id: Ice06b67aeaa3bb8f36a6d3721014888defbfac15
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Create the moxoe variant of the moxie project by
copying the files to a new directory named for the variant.
BUG=b:481186489
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXOE
Change-Id: I5dd9cc21b647834144cfffcd43bdcf84e9df3a0c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.
It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.
Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.
TEST=Lenovo X220 still boots.
Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the same wakeup method that Meteor Lake uses to Panther Lake.
TEST=Able to build and boot google/moonstone where able to wake
the device using differnt USB devices like USB FP, KB and Mouse.
Change-Id: Id680b443791c3dbc502d1b6776fd0fa03bd80691
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit adds a wake configuration to the cnvi_bluetooth device for
the ruby variant. The "wake" setting is now registered to "GPE0_PME_B0"
using the common CNVi block. This enhancement ensures that the
cnvi_bluetooth device can properly wake the system.
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: If1b3af2a9ad8c3e3800f5c839190727d78122853
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
When disabling slow battery charging, explicitly set the Fast Charge
Current (FCC) configuration to 0x8c (disable) for both SMB1 and SMB2
controllers.
This ensures that the PMIC charging registers are returned to a
neutral/safe state while disabling the charging.
BUG=b:481546101
TEST=Build and boot Bluey. Verified that SMB1/SMB2_CHGR_MAX_FCC_CFG
registers are cleared during the disable_slow_battery_charging call.
Change-Id: Ic5da492b097747dec88b117ac021759644b8b816
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91121
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the juchi variant of the jubilant project by
copying the files to a new directory named for the variant.
BUG=b:481602501
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_JUCHI.
Change-Id: I4a1919f6a2480e4e2f993fa24658836a1739714c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
This adds generate_font.py, a Python utility designed to convert
standard TTF/OTF files into a compact bitmapped format suitable for
firmware framebuffers.
Key features:
- Generates a left-aligned (normalized) bitmapped table to eliminate
dead space in font glyphs.
- Outputs a character width table to support proportional spacing.
- Exports FONT_HEIGHT and FONT_WIDTH macros for C synchronization.
- Limits output to printable ASCII (32-126) to minimize binary bloat.
The tool uses the Pillow (PIL) library to rasterize glyphs and is
intended to be used during the build process to generate C source
files for splash screen text rendering.
Usage:
python util/font/generate_font.py <font.ttf> > font_table.c
Change-Id: Iec8907f1a5f24d61822230f6a22295c8382d2229
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Remove the sa_get_tseg_size() function and replace all its usage with
CONFIG_SMM_TSEG_SIZE configuration option. The TSEG size is now
obtained directly from the configuration instead of being calculated
dynamically. The existing calculation assumes GSM and TSEG regions are
contiguous, but there is no guarantee this is always true depending on
how FSP operates. This could lead to incorrect size calculations.
Using CONFIG_SMM_TSEG_SIZE is more reliable as this value is provided
to the FSP during initialization.
This change:
- Removes sa_get_tseg_size() function declaration and implementation
- Updates smm_region() to use CONFIG_SMM_TSEG_SIZE directly
- Updates Alder Lake, Meteor Lake, and Panther Lake system agent code
to use CONFIG_SMM_TSEG_SIZE instead of sa_get_tseg_size()
Before (sa_get_tseg_size):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] sa_get_tseg_size:0x3c00000
[DEBUG] New SMBASE=0x7b5ec000 IEDBASE=0x7b800000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfc400c00
System hangs during SMM relocation
After (CONFIG_SMM_TSEG_SIZE):
[SPEW ] TsegBase = 0x78000000
[SPEW ] GsmBase = 0x7BC00000
[DEBUG] CONFIG_SMM_TSEG_SIZE:0x2000000
[DEBUG] New SMBASE=0x799ec000 IEDBASE=0x79c00000
[DEBUG] Writing SMRR. base = 0x78000006, mask=0xfe000c00
[DEBUG] Relocation complete.
System boots successfully
BUG=none
Change-Id: Ie2a1f3dd68941924e056a12f01857c1182b69198
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91063
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update fast_vmode_i_trip array references as per 813278_Rev2p1p1 to use
PTL_SKU_* constants instead of PTL_CORE_* constants. This aligns with
the corrected indexing scheme used in the SoC VR configuration code.
TEST=Verify IccLimit value for different SKUs in FSP debug log
Change-Id: I90a5c6e03633ba2b4a0a132ed9f94d8e5c4ff8bf
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91049
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add documentation for the Intel PCH Top Swap based A/B redundancy
mechanism. Describe the BOOTBLOCK and TOPSWAP bootblock regions,
COREBOOT and COREBOOT_TS CBFS regions, the attempt_slot_b CMOS option
and its application time, and how the active CBFS region is selected
based on the Top Swap state.
This follows the A/B redundancy proposal discussed on the coreboot
mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Change-Id: I1b88989201e209b2f69964c067c432ff82a0057e
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90412
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the infrastructure required to display an off-mode charging
notification. This is used when a device boots due to power cable
insertion but should remain in a charging state rather than booting
the full operating system.
Changes:
- Add BOOTSPLASH_OFF_MODE_CHARGING to bootsplash_type.
- Define platform_is_off_mode_charging_active() with a weak inline
fallback to allow platforms to signal off-mode charging status.
- Update bmp_logo.c to recognize "off_mode_charging.bmp" and select
it as the active logo type when charging is active.
- Modify render_bmp.c to handle layout and rendering for the charging
logo, including support for footer text if enabled.
- Ensure the rendering flow bails out early after displaying the
charging notification to prevent standard OS boot splash.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ief4c65eaf0178ff3d736363c3e56acfe1adba14a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce CONFIG_PLATFORM_HAS_OFF_MODE_CHARGING_INDICATOR to support
rendering a dedicated splash screen when a device is in an off-mode
charging state. This provides visual feedback to the user when a
device autoboots upon power cable insertion instead of performing
a full OS boot.
Changes:
- Add Kconfig options for enabling the indicator and specifying
the logo path.
- Update Makefile.mk to include the off-mode charging BMP file
in CBFS when the feature is enabled.
- Depend on BMP_LOGO infrastructure for asset rendering.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ib09de15ca3526bf5b10f7404dc58032d63c01e6d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit increases the default pre-allocated IGD stolen memory size
from 64MB to 128MB in FSP-M parameters. This ensures sufficient memory
is allocated for higher resolution displays and graphics-intensive
early-boot tasks on Panther Lake platforms.
BUG=b:481209815
TEST=Able to build and boot google/ruby.
Change-Id: Idd3f1bcb9cbb27adc18a31c0dd5952e901ecf5eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91126
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the Integrated Graphics Device (IGD) stolen memory size enum
values to align with the Panther Lake Reference Code. This change
introduces the 96MB definition and corrects the value for 128MB.
Modified values:
- IGD_SM_96MB: Added as 0x03
- IGD_SM_128MB: Updated from 0x03 to 0x04
Change-Id: Id7a547e8a530294a76f201e87865e8508ff67a92
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91140
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ancient microcode update files do not have a total_size field.
Add support for such platforms and return 2048 in that case.
Change-Id: I952edc12cccf24f396d940bc594d8ef97826a253
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90910
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set CBFS_SIZE to match the SI_BIOS region size defined in each board's
chromeos.fmd file, up to a maximum of 16MiB. This ensures the largest
possible region is available for CBFS use without requiring manual
CBFS_SIZE overrides. The size is capped at 16MiB as that is the
largest area that can be memory mapped, the FIT pointer must be
located in the top 16MiB.
This change applies to all Intel-based Google mainboards with ChromeOS
FMD layouts that explicitly define SI_BIOS region sizes, and which do
not define a default non-ChromeOS FMAP layout (octopus, reef).
For boards with multiple ChromeOS FMD files, CBFS_SIZE is set
conditionally based on ROM size or silicon variant, using the
same logic as to select the ChromeOS FMD file.
This eliminates the need to override CBFS_SIZE when using larger
payloads (e.g., edk2) or multiple payloads, making the default
configuration more flexible.
TEST=build/boot various google boards with edk2 payload without
overriding CBFS_SIZE.
Change-Id: If7ef6cc96afcdd025958c578ad80fd0db641582a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This solves the remark:
```
dsdt.asl 28: Name (RBUF, ResourceTemplate ()
Remark 2173 - ^ Creation of named objects within a method is highly inefficient, use globals or method local variables instead (\_SB.PERC._CRS)
```
Change-Id: Ifff2678e351cf6d92a7fba5d3cf64413e15393c0
Signed-off-by: Evie (Ivi) Ballou <iviballou@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On these two mainboards, a Gen1 device is connected on PCIe RP #7.
Measurements have shown that a value of -0.137 dB yields an optimal eye
TX mask test.
BUG=none
TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope
Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides support for board-specific fine-tuning of PCIe root
ports.
The following parameters can be adjusted.
PchPcieHsioTxGen1DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 1
PCIe devices
PchPcieHsioTxGen2DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 2
PCIe devices
PchPcieHsioTxGen3DownscaleAmp:
- Adjust the transmitter driver strength and its output swing for Gen 3
PCIe devices
PchPcieHsioTxGen1DeEmph:
- Adjust or fine-tune the amount for PCIe Gen 1 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph3p5:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -3.5dB mode
PchPcieHsioTxGen2DeEmph6p0:
- Adjust or fine-tune the amount for PCIe Gen 2 devices by which the
output is de-emphasized for -6.0dB mode
Change-Id: I7b51de2b7f75e15d902e471a19b8b29166ddfb48
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Change the HID used from OVTIDB10 to OVTI13B1 for proper attachment
under Windows. Linux/ChromeOS don't use the HID, and so are unaffected
by the change.
TEST=build/boot Win11 on Teliks, verify MIPI camera driver loads
properly.
Change-Id: Ia81bd8cfaf6bb160f4f18214edccdf425d22cf6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91108
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the corresponding sensor_name value used by the Windows drivers for
each camera sensor. Update the name used for Redrix based on testing.
This value is not used by ChromeOS/Linux.
TEST=build/boot Win11 on redrix, magolor. Verify IPU/MIPI camera works
properly using available drivers.
Change-Id: Id4fba3667f9497f71787e504bf244d54e433e552
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Adjust the option groups into more logical groups, and ensure all
are alphabetised.
Change-Id: I8bac31206e16146ce55c3946fa8e8e4accdc7060
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91112
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The descriptor was updated to support Raptor Lake upgrades, which
increased the ME region size.
Change-Id: I0fa909e8aa58c8825fb9cd0301e9bbc60cf1ca89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached.
This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer
writes.
Ensure BAR ranges get a cacheable attribute instead of falling back to
UC.
Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the local LOW_BATTERY_SHUTDOWN_DELAY_SEC macro with the newly
introduced, globally configurable PLATFORM_POST_RENDER_DELAY_SEC
Kconfig.
This aligns the bluey mainboard with the shared platform delay logic,
ensuring a consistent user experience across products while allowing
easier adjustment of the shutdown/teardown timing buffer.
TEST=Verified build and boot on bluey; critical battery shutdown still
respects the intended 5-second delay (as per default Kconfig).
Change-Id: I1ddab276e797b793974e0205a91ba832f3085ead
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The existing PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC was strictly
tied to the low-battery indicator logic. This change renames and
generalizes the configuration to PLATFORM_POST_RENDER_DELAY_SEC.
By moving this out of the low-battery specific conditional block in
Kconfig, the delay can now be utilized more broadly. While it still
ensures the low-battery warning remains visible before power-off, it
can now also be used to ensure display synchronization or user
notifications are visible before passing control to the OS in normal
boot flows.
Updated Intel common reset logic to utilize the renamed config.
BUG=b:473480933
TEST=Verified that low-battery shutdown still respects the 5-second
default delay on target hardware.
Change-Id: I0277ea278fb299499f6eab2be983761a8f6ba536
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91104
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'const' qualifier is unnecessary for the return values of the
following:
- list_next()
- list_prev()
- list_first()
- list_last()
Therefore, drop it. No caller needs to be changed.
Change-Id: I0f5bc2b0ed3cd47d0d6355c8dffea17f6e085407
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91113
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Support for the rex touchscreen panel was needed for the RVP to validate touchscreen functionality. The LPSS touchscreen is mapped to I2C bus 4 and the rex panel is mapped to address 0x10.
BUG=b:458429110
TEST=None
Change-Id: I99b2c7beaab63da1877995c655ff8eddf9c3a69f
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.
No functional change, thus untested.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.
Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME
Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras
Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).
For more information please refer to #854345 (Intel CNDA).
Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree.
BUG=b:481143310
TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design.
Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The Matsu hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=443612246
TEST=Build and boot to OS on Matsu, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I84db81c17afffafbdb6c7abcc752009c824bc2ed
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91086
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The Kinmen hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=460038237
TEST=Build and boot to OS on Kinmen, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I5e20c247bd45427f817e7afd8355a71c7a9c161c
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
