mb/google/brya: Create kulnex variant
Create the kulnex variant of the kuldax project by copying the files to a new directory named for the variant. BUG=b:480035819 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KULNEX Change-Id: Ice06b67aeaa3bb8f36a6d3721014888defbfac15 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
This commit is contained in:
David Wu
Matt DeVillier
parent
f6f4217bfd
commit
f0bc0a5999
11 changed files with 682 additions and 0 deletions
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@ -359,6 +359,13 @@ config BOARD_GOOGLE_KULDAX
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_RAPTORLAKE
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config BOARD_GOOGLE_KULNEX
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select BOARD_GOOGLE_BASEBOARD_BRASK
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select DRIVERS_GENESYSLOGIC_GL9755
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select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
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select INTEL_GMA_HAVE_VBT
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select SOC_INTEL_RAPTORLAKE
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config BOARD_GOOGLE_JOXER
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select CHROMEOS_WIFI_SAR if CHROMEOS
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@ -873,6 +880,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_KALADIN
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default 0x1 if BOARD_GOOGLE_KINOX
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default 0x1 if BOARD_GOOGLE_KULDAX
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default 0x1 if BOARD_GOOGLE_KULNEX
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default 0x1 if BOARD_GOOGLE_LISBON
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default 0x1 if BOARD_GOOGLE_MARASOV
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default 0x1 if BOARD_GOOGLE_MITHRAX
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@ -962,6 +970,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_KALADIN
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default 13 if BOARD_GOOGLE_KINOX
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default 13 if BOARD_GOOGLE_KULDAX
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default 13 if BOARD_GOOGLE_KULNEX
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default 13 if BOARD_GOOGLE_LISBON
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default 13 if BOARD_GOOGLE_MARASOV
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default 13 if BOARD_GOOGLE_MITHRAX
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@ -1055,6 +1064,7 @@ config MAINBOARD_PART_NUMBER
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default "Kaladin" if BOARD_GOOGLE_KALADIN
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default "Kinox" if BOARD_GOOGLE_KINOX
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default "Kuldax" if BOARD_GOOGLE_KULDAX
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default "Kulnex" if BOARD_GOOGLE_KULNEX
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default "Lisbon" if BOARD_GOOGLE_LISBON
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default "Marasov" if BOARD_GOOGLE_MARASOV
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default "Mithrax" if BOARD_GOOGLE_MITHRAX
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@ -1137,6 +1147,7 @@ config VARIANT_DIR
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default "kaladin" if BOARD_GOOGLE_KALADIN
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default "kinox" if BOARD_GOOGLE_KINOX
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default "kuldax" if BOARD_GOOGLE_KULDAX
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default "kulnex" if BOARD_GOOGLE_KULNEX
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default "lisbon" if BOARD_GOOGLE_LISBON
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default "marasov" if BOARD_GOOGLE_MARASOV
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default "mithrax" if BOARD_GOOGLE_MITHRAX
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@ -95,6 +95,9 @@ config BOARD_GOOGLE_KINOX
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config BOARD_GOOGLE_KULDAX
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bool "-> Kuldax (ASUS Chromebox 5/5a (CN67))"
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config BOARD_GOOGLE_KULNEX
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bool "-> Kulnex"
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config BOARD_GOOGLE_JOXER
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bool "-> Joxer (HP Chromebook x360 14b)"
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9
src/mainboard/google/brya/variants/kulnex/Makefile.mk
Normal file
9
src/mainboard/google/brya/variants/kulnex/Makefile.mk
Normal file
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += ramstage.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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BIN
src/mainboard/google/brya/variants/kulnex/data.vbt
Normal file
BIN
src/mainboard/google/brya/variants/kulnex/data.vbt
Normal file
Binary file not shown.
75
src/mainboard/google/brya/variants/kulnex/fw_config.c
Normal file
75
src/mainboard/google/brya/variants/kulnex/fw_config.c
Normal file
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@ -0,0 +1,75 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config dmic_enable_pads[] = {
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
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};
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static const struct pad_config dmic_disable_pads[] = {
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PAD_NC(GPP_R6, NONE),
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PAD_NC(GPP_R7, NONE),
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};
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static const struct pad_config i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
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};
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static const struct pad_config i2s_disable_pads[] = {
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PAD_NC(GPP_R0, NONE),
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PAD_NC(GPP_R1, NONE),
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PAD_NC(GPP_R2, NONE),
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PAD_NC(GPP_R3, NONE),
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};
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static const struct pad_config bt_i2s_enable_pads[] = {
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
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};
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static const struct pad_config bt_i2s_disable_pads[] = {
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PAD_NC(GPP_VGPIO_30, NONE),
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PAD_NC(GPP_VGPIO_31, NONE),
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PAD_NC(GPP_VGPIO_32, NONE),
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PAD_NC(GPP_VGPIO_33, NONE),
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PAD_NC(GPP_VGPIO_34, NONE),
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PAD_NC(GPP_VGPIO_35, NONE),
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PAD_NC(GPP_VGPIO_36, NONE),
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PAD_NC(GPP_VGPIO_37, NONE),
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};
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static void fw_config_handle(void *unused)
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{
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if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
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printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
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gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
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gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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return;
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}
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if (fw_config_probe(FW_CONFIG(AUDIO, NAU88L25B_I2S))) {
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printk(BIOS_INFO, "Configure audio over I2S with NAU88L25B.\n");
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gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
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gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
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printk(BIOS_INFO, "BT offload enabled\n");
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gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
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} else {
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printk(BIOS_INFO, "BT offload disabled\n");
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gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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133
src/mainboard/google/brya/variants/kulnex/gpio.c
Normal file
133
src/mainboard/google/brya/variants/kulnex/gpio.c
Normal file
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@ -0,0 +1,133 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A14 : USB_OC1# ==> HDMIA_HPD */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF2),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
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PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
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/* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
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PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
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/* C3 : SML0CLK ==> USB_C0_AUX_DC_P */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF6),
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/* C4 : SML0DATA ==> USB_C0_AUX_DC_N */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF6),
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/* D0 : ISH_GP0 ==> NC */
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PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
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/* D1 : ISH_GP1 ==> NC */
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PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
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/* D2 : ISH_GP2 ==> NC */
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PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
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/* F12 : GSXDOUT ==> NC */
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PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
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/* F13 : GSXDOUT ==> NC */
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PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
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/* F15 : GSXSRESET# ==> NC */
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PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
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/* F16 : GSXCLK ==> NC */
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PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
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/* R4 : HDA_RST# ==> NC */
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PAD_NC(GPP_R4, NONE),
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/* R5 : HDA_SDI1 ==> NC */
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PAD_NC(GPP_R5, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H13 : I2C7_SCL ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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354
src/mainboard/google/brya/variants/kulnex/overridetree.cb
Normal file
354
src/mainboard/google/brya/variants/kulnex/overridetree.cb
Normal file
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@ -0,0 +1,354 @@
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fw_config
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field AUDIO 0 2
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option AUDIO_UNKNOWN 0
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option NAU88L25B_I2S 1
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end
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field BJ_POWER 3 4
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option BJ_POWER_150W 0
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option BJ_POWER_230W 1
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option BJ_POWER_65W 2
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option BJ_POWER_135W 3
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end
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field MB_USBC 6 7
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option TC_USB4 0
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option TC_USB3 1
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end
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field USB_HUB 32
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option HUB_ABSENT 0
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option HUB_PRESENT 1
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end
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end
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chip soc/intel/alderlake
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register "domain_vr_config[VR_DOMAIN_IA]" = "{
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.enable_fast_vmode = 1,
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}"
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register "sagv" = "SaGv_Enabled"
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
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register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2
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||||
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
|
||||
|
||||
register "usb3_ports[0]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC_SKIP,
|
||||
.tx_de_emp = 0x2B,
|
||||
.tx_downscale_amp = 0x00,
|
||||
}" # Type-A port A0
|
||||
register "usb3_ports[1]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC_SKIP,
|
||||
.tx_de_emp = 0x2B,
|
||||
.tx_downscale_amp = 0x00,
|
||||
}" # Type-A port A1
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_A] = DDI_ENABLE_HPD,
|
||||
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
[DDI_PORT_1] = DDI_ENABLE_HPD,
|
||||
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
}"
|
||||
|
||||
register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
.tdp_pl2_override = 55,
|
||||
.tdp_pl4 = 100,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DRAM""
|
||||
register "options.tsr[1].desc" = ""Charger""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(85, 90),
|
||||
TEMP_PCT(80, 80),
|
||||
TEMP_PCT(75, 70),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
|
||||
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 3000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 55000,
|
||||
.max_power = 55000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# Enable CPU PCIE RP 1 using CLK 0
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_req = 0,
|
||||
.clk_src = 0,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "is_storage" = "true"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
|
||||
register "srcclk_pin" = "0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tbt_pcie_rp0 on
|
||||
probe MB_USBC TC_USB4
|
||||
end
|
||||
device ref tbt_pcie_rp1 on
|
||||
probe MB_USBC TC_USB4
|
||||
end
|
||||
device ref tbt_pcie_rp2 on
|
||||
probe MB_USBC TC_USB4
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
probe MB_USBC TC_USB4
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/nau8825
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A23)"
|
||||
register "jkdet_enable" = "1"
|
||||
register "jkdet_pull_enable" = "0"
|
||||
register "jkdet_pull_up" = "0"
|
||||
register "jkdet_polarity" = "1" # ActiveLow
|
||||
register "vref_impedance" = "2" # 125kOhm
|
||||
register "micbias_voltage" = "6" # 2.754
|
||||
register "sar_threshold_num" = "4"
|
||||
register "sar_threshold[0]" = "0x0C"
|
||||
register "sar_threshold[1]" = "0x1C"
|
||||
register "sar_threshold[2]" = "0x38"
|
||||
register "sar_threshold[3]" = "0x60"
|
||||
register "sar_hysteresis" = "1"
|
||||
register "sar_voltage" = "0" # VDDA
|
||||
register "sar_compare_time" = "0" # 500ns
|
||||
register "sar_sampling_time" = "0" # 2us
|
||||
register "short_key_debounce" = "2" # 100ms
|
||||
register "jack_insert_debounce" = "7" # 512ms
|
||||
register "jack_eject_debounce" = "7" # 512ms
|
||||
device i2c 1a on
|
||||
probe AUDIO NAU88L25B_I2S
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
chip drivers/net
|
||||
register "wake" = "GPE0_DW0_07"
|
||||
register "led_feature" = "0xe0"
|
||||
register "customized_leds" = "0x05af"
|
||||
register "customized_led0" = "0x23f"
|
||||
register "customized_led2" = "0x028"
|
||||
register "enable_aspm_l1_2" = "1"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # RTL8125 and RTL8111K Ethernet NIC
|
||||
device ref pcie_rp8 on
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
end #PCIE8 SD card
|
||||
device ref gspi1 off end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A3 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A2 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb2_port9 on
|
||||
probe USB_HUB HUB_ABSENT
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Hub for Type-A Port A0/A4/A5 (MLB)""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port9 on
|
||||
probe USB_HUB HUB_PRESENT
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))"
|
||||
device ref usb3_port1 on
|
||||
probe USB_HUB HUB_ABSENT
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Hub for Type-A Port A0/A4/A5 (MLB)""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port1 on
|
||||
probe USB_HUB HUB_PRESENT
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A2 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A3 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 1))"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
58
src/mainboard/google/brya/variants/kulnex/ramstage.c
Normal file
58
src/mainboard/google/brya/variants/kulnex/ramstage.c
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <fw_config.h>
|
||||
#include <intelblocks/power_limit.h>
|
||||
|
||||
const struct cpu_power_limits limits[] = {
|
||||
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
|
||||
{ PCI_DID_INTEL_RPL_P_ID_5, 15, 15000, 15000, 55000, 55000, 100000 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 15000, 55000, 55000, 100000 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 15000, 55000, 55000, 100000 },
|
||||
};
|
||||
|
||||
const struct system_power_limits sys_limits[] = {
|
||||
/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
|
||||
{ PCI_DID_INTEL_RPL_P_ID_5, 15, 138 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 138 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 138 },
|
||||
};
|
||||
|
||||
/*
|
||||
* Psys_pmax considerations.
|
||||
*
|
||||
* Given the hardware design in kulnex, the serial shunt resistor is 0.005ohm.
|
||||
* The full scale of hardware PSYS signal 1.6v maps to system current 11.25A
|
||||
* instead of real system power. The equation is shown below:
|
||||
* PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510)
|
||||
* R501/(R501 + R510) = 0.57 = 20K / (20K + 15K)
|
||||
*
|
||||
* The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input
|
||||
* current and the actual system power. Since there is no voltage information
|
||||
* from PSYS, different voltage input would map to different Psys_pmax settings:
|
||||
* For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W
|
||||
* For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W
|
||||
* For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W
|
||||
*
|
||||
* Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
|
||||
* and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system
|
||||
* power = 225W * 5A / 11.25A = 100W, which is the actual system power.
|
||||
*/
|
||||
const struct psys_config psys_config = {
|
||||
.efficiency = 97,
|
||||
.psys_imax_ma = 11250,
|
||||
.bj_volts_mv = 20000
|
||||
};
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
size_t total_entries = ARRAY_SIZE(limits);
|
||||
variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
|
||||
|
||||
variant_update_power_limits(limits, total_entries);
|
||||
}
|
||||
23
src/mainboard/google/brya/variants/kulnex/variant.c
Normal file
23
src/mainboard/google/brya/variants/kulnex/variant.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return "wifi_sar_0.hex";
|
||||
}
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
|
||||
NAU88L25B_I2S));
|
||||
|
||||
if (fw_config_probe(FW_CONFIG(MB_USBC, TC_USB3))) {
|
||||
config->tcss_aux_ori = 1;
|
||||
config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_C3;
|
||||
config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_C4;
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue