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mainboard/intel: Add PantherLake CRB for Edge

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This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.

Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME

Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras

Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).

For more information please refer to #854345 (Intel CNDA).

Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Alicja Michalska 2025-08-06 05:04:14 +02:00 • committed by Matt DeVillier
commit 8954bd72a9
13 changed files with 735 additions and 0 deletions
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58
src/mainboard/intel/pantherlake_crb/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_INTEL_PANTHERLAKE_CRB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select CPU_INTEL_SOCKET_OTHER
select CRB_TPM
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC if SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
select DRIVERS_GFX_GENERIC
select DRIVERS_I2C_GENERIC
select DRIVERS_USB_ACPI
select DRIVERS_SPI_ACPI
select DUMP_SMBIOS_TYPE17
select GENERATE_SMBIOS_TABLES
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_INTEL_PTT
select INTEL_GMA_HAVE_VBT
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_GBE_REGION
select MAINBOARD_USES_IFD_EC_REGION
select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select AZALIA_USE_LEGACY_VERB_TABLE
select SOC_INTEL_COMMON_BLOCK_MEMINIT
select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_PANTHERLAKE_H
select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
select SUPERIO_ITE_IT8659E
# To be removed when we receive production SKUs for testing
select SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON
select FSP_UGOP_EARLY_SIGN_OF_LIFE
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "PantherLake CRB"
config MAINBOARD_DIR
default "intel/pantherlake_crb"
config MAINBOARD_PART_NUMBER
default "PantherLake CRB"
config CBFS_SIZE
default 0xA00000
config USE_PM_ACPI_TIMER
default n
endif

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src/mainboard/intel/pantherlake_crb/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_INTEL_PANTHERLAKE_CRB
bool "Intel PantherLake CRB for Edge"

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src/mainboard/intel/pantherlake_crb/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
ramstage-y += ramstage.c
romstage-y += romstage.c

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src/mainboard/intel/pantherlake_crb/board.fmd Normal file
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FLASH 32M {
SI_ALL 18M {
SI_DESC 16K
SI_EC 576K
SI_GBE 8K
SI_ME
SI_PDR 4K
}
SI_BIOS 14M {
UNIFIED_MRC_CACHE(PRESERVE) 256K {
RECOVERY_MRC_CACHE 128K
RW_MRC_CACHE 128K
}
SMMSTORE(PRESERVE) 256K
CONSOLE 128K
RW_VPD(PRESERVE) 32K
FMAP 2K
COREBOOT(CBFS)
}
}

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src/mainboard/intel/pantherlake_crb/board_info.txt Normal file
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Vendor name: Intel
Board name: PantherLake CRB
Category: eval
ROM protocol: SPI
ROM socketed: y
Flashrom support: y

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src/mainboard/intel/pantherlake_crb/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/gpio.h>
#include <device/pnp_ops.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8659e/it8659e.h>
#include "gpio.h"
#define UART_DEV PNP_DEV(0x4e, IT8659E_SP1)
#define GPIO_DEV PNP_DEV(0x4e, IT8659E_GPIO)
void bootblock_mainboard_early_init(void)
{
// Early eSPI and LPSS UART initialization
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
ite_reg_write(GPIO_DEV, 0x26, 0xc0);
ite_reg_write(GPIO_DEV, 0x29, 0x24);
ite_reg_write(GPIO_DEV, 0x2c, 0x88);
// COM1 (CP2105 Port B)
ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
}

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src/mainboard/intel/pantherlake_crb/data.vbt Normal file
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src/mainboard/intel/pantherlake_crb/devicetree.cb Normal file
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chip soc/intel/pantherlake
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
device domain 0 on
device ref igpu on
# DDI-A: DP, DDI-B: Unused, DDI-C: Unused
# DDI-1: TCP-0, DDI-2: TCP-1, DDI-3: TCP-2, DDI-4: TCP-4
register "ddi_port_A_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
# TODO: IPU Cameras. Currently no modules available.
# GbE LAN
device ref gbe on
register "pcie_rp[PCIE_RP(1)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
register "pcie_clk_config_flag[3]" = "PCIE_CLK_LAN"
end
# M.2 WWAN (untested)
device ref pcie_rp2 on
register "pcie_rp[PCIE_RP(2)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
end
# Gen4 x1 slot
device ref pcie_rp3 on
register "pcie_rp[PCIE_RP(3)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
end
# M.2 WiFi
device ref pcie_rp4 on
register "pcie_rp[PCH_RP(4)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "4"
device pci 00.0 on end
end
chip drivers/wifi/generic
register "add_acpi_dma_property" = "true"
register "wake" = "GPE0_DW0_12" # GPP_A12
use usb2_port7 as bluetooth_companion
device pci 00.0 on end
end
end
# M.2 SSD Gen4
device ref pcie_rp5 on
register "pcie_rp[PCIE_RP(5)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B10)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B09)"
register "srcclk_pin" = "6"
device generic 0 on end
end
end
# PEG Gen5 x4 slot (M.2 SSD Gen5 with rework)
device ref pcie_rp9 on
register "pcie_rp[PCIE_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
end
# PEG Gen5 x8 slot (available only on PTL-H484)
device ref pcie_rp11 on
register "pcie_rp[PCIE_RP(11)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
}"
end
# TODO: Thunderbolt. No AIC modules available at the moment.
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tcss_xhci on end
# TODO: Type-C role switch
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_TYPE_C(OC3), // Type-C P0
[1] = USB2_PORT_TYPE_C(OC3), // Type-C P1
[2] = USB2_PORT_TYPE_C(OC6), // Type-C P2
[3] = USB2_PORT_TYPE_C(OC7), // Type-C P3
[4] = USB2_PORT_MID(OC0), // Type-A P1
[5] = USB2_PORT_MID(OC0), // Type-A P2
[6] = USB2_PORT_MID(OC_SKIP), // M.2 WWAN
[7] = USB2_PORT_MID(OC_SKIP), // M.2 NGFF (BT)
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC0), // Type-C P1
[1] = USB3_PORT_DEFAULT(OC0), // Type-C P2
}"
end
# CNVi (Untested: lack of hardware).
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
use cnvi_bluetooth as bluetooth_companion
device generic 0 on end
end
end
device ref cnvi_bluetooth on
chip soc/intel/common/block/cnvi
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref npu on end
# Likely broken on pre-production silicon?
# Linux freaks out if it's enabled.
device ref iaa off end
# I2C interfaces
device ref i2c0 on
# TODO: PD Controller
## Port-A @ 0x20
## Port-B @ 0x24
# TODO: TCSS1
# TODO: TCSS2
# TODO: TTK3 @ 0x70
# TODO: POST_LED @ 0x38
# TODO: 1x3 HDR
end
device ref i2c1 on
# TODO: IPU CARD 1
end
device ref i2c2 on
# TODO: IPU CARD 2
end
device ref i2c3 on
# TODO: AUDIO HDR: 0x1a, 0x28, 0x19, 0x2a, 0x2b
end
device ref i2c4 on
# TODO: DP Repeater @ (0x08, 0x17)?
# TODO: VBY1 HDR @ 0x48
end
device ref i2c5 on end
# LPSS UART interfaces
device ref uart0 on end # USB-TTL Bridge (Port A).
device ref uart1 on end # J17 header.
device ref uart2 on end # J7 header.
## UART0 will fail to initialize on pre-production silicon if set to "Pci"!
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoHidden,
[PchSerialIoIndexUART2] = PchSerialIoHidden,
}"
register "serial_io_uart_dma_enable" = "{
[PchSerialIoIndexUART0] = PchSerialDma,
[PchSerialIoIndexUART1] = PchSerialDma,
[PchSerialIoIndexUART2] = PchSerialDma,
}"
# ITE IT8659E SuperIO
device ref soc_espi on
chip superio/ite/it8659e
device pnp 4e.1 on # COM1: USB-TTL bridge (Port B)
io 0x60 = 0x3f8
irq 0x70 = 0x04
irq 0xf0 = 0x01
irq 0xf1 = 0x50
irq 0xf2 = 0x00
end
device pnp 4e.2 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 0x03
irq 0xf0 = 0x00
irq 0xf1 = 0x50
irq 0xf2 = 0x00
end
device pnp 4e.4 on # EC
io 0x60 = 0x290
io 0x62 = 0x230
irq 0x70 = 0x00
irq 0xf0 = 0x80
irq 0xf1 = 0x40
irq 0xf6 = 0xf0
end
device pnp 4e.5 off end # PS/2 KB
device pnp 4e.6 off end # PS/2 MS
device pnp 4e.7 on # GPIO
io 0x60 = 0x000
io 0x62 = 0x000
irq 0x26 = 0xc0
irq 0x29 = 0x24
irq 0x2c = 0x88
irq 0x72 = 0x80
irq 0xb8 = 0x00
irq 0xbc = 0x20
irq 0xcb = 0x00
irq 0xe7 = 0x10
irq 0xf0 = 0x10
irq 0xf1 = 0x40
irq 0xf4 = 0x2d
irq 0xf6 = 0x0e
end
device pnp 4e.a off end # CIR
end
end
# TODO: Realtek ALC722-CG Audio. DSP firmware not upstreamed into Linux yet.
device ref hda on
register "pch_hda_dsp_enable" = "true"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "true"
end
device ref pmc_shared_sram on end
device ref smbus on end
end
end

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src/mainboard/intel/pantherlake_crb/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
// HACK: MISCCFG_GPIO_PM_CONFIG_BITS are missing
#include <acpi/acpi.h>
#include <soc/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20240917
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0) {
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/pantherlake/acpi/southbridge.asl>
#include <soc/intel/pantherlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

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src/mainboard/intel/pantherlake_crb/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <soc/gpio.h>
/* GPIOs configured in bootblock */
static const struct pad_config early_gpio_table[] = {
// eSPI: IT8659E SuperIO
PAD_CFG_NF(GPP_A00, NONE, DEEP, NF1), // ESPI_IO0_SIO_R
PAD_CFG_NF(GPP_A01, NONE, DEEP, NF1), // ESPI_IO1_SIO_R
PAD_CFG_NF(GPP_A02, NONE, DEEP, NF1), // ESPI_IO2_SIO_R
PAD_CFG_NF(GPP_A03, NONE, DEEP, NF1), // ESPI_IO3_SIO_R
PAD_CFG_NF(GPP_A04, NONE, DEEP, NF1), // ESPI_CS0_SIO_R_N
PAD_CFG_NF(GPP_A05, NONE, DEEP, NF1), // ESPI_CLK_SIO
PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RST_SIO_R_N
PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), // ESPI_ALERT_SIO_R_N
// LPSS UART0: USB TTL bridge
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // RXD
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // TXD
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // RTS
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // CTS
// LPSS UART1: J17 header
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF2), // TXD
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF2), // RXD
// LPSS UART2: J7 header
PAD_CFG_NF(GPP_F00, NONE, DEEP, NF2), // RTS
PAD_CFG_NF(GPP_F01, NONE, DEEP, NF2), // RXD
PAD_CFG_NF(GPP_F02, NONE, DEEP, NF2), // TXD
PAD_CFG_NF(GPP_F03, NONE, DEEP, NF2), // CTS
};
/* GPIOs configured in romstage */
static const struct pad_config main_gpio_table[] = {
/* GPIO Community A */
PAD_CFG_GPO(GPP_A08, 1, PLTRST), // X1_PCIE_SLOT_PWR_EN
PAD_CFG_GPO(GPP_A09, 0, DEEP), // M.2_WWAN_FCP_OFF_N
PAD_CFG_GPO(GPP_A10, 0, DEEP), // M.2_WWAN_DISABLE_N
PAD_CFG_GPO(GPP_A11, 1, PLTRST), // WLAN_RST_N
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), // WLAN_WAKE_N
PAD_CFG_NF(GPP_A13, NONE, PLTRST, NF1), // WWAN_DPR
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), // DNX_FORCE_RELOAD
PAD_CFG_GPO(GPP_A16, 1, DEEP), // BT_RF_KILL_N
PAD_CFG_GPO(GPP_A17, 1, DEEP), // WIFI_RF_KILL_N
/* GPIO Community B */
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), // USB-C SMLCLK
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), // USB-C SMLDATA
PAD_CFG_NF(GPP_B02, NONE, DEEP, NF3), // CAM1_ISH_I2C_SDA
PAD_CFG_NF(GPP_B03, NONE, DEEP, NF3), // CAM1_ISH_I2C_SCL
PAD_CFG_GPO(GPP_B04, 0, DEEP), // VBY1_BKLTCTRL_3P3V
PAD_CFG_GPO(GPP_B05, 0, DEEP), // VBY1_GPIO2_3P3V
PAD_CFG_GPO(GPP_B06, 0, DEEP), // VBY1_GPIO1_3P3V
PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), // ALC722 PCBEEP
PAD_CFG_GPO(GPP_B08, 0, DEEP), // VBY1_GPIO0_3P3V
PAD_CFG_GPO(GPP_B09, 1, PLTRST), // M2_GEN4_SSD_RESET_N
PAD_CFG_GPO(GPP_B10, 0, PLTRST), // M2_GEN4_SSD_PWR_DIS
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // MOD_TCSS1_DISP_HPD3
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // PM_SLP_S0_N
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST_N
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), // MOD_TCSS2_DISP_HPD4
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), // MOD_TCSS1_USB_TYP_A_OC3_N
PAD_CFG_GPO(GPP_B16, 0, PLTRST), // X4_PCIE_SLOT_PWR_EN_N
PAD_NC(GPP_B17, NONE), // N/C
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), // DDIA_RDVR_I2C_DATA
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), // DDIA_RDVR_I2C_CLK
PAD_CFG_GPO(GPP_B20, 1, PLTRST), // M.2_WWAN_RST_BUF_N
PAD_CFG_GPO(GPP_B21, 0, DEEP), // TCP_RETIMER_FORCE_PWR
PAD_CFG_GPO(GPP_B22, 0, PLTRST), // TIME_SYNC0
PAD_CFG_GPO(GPP_B23, 0, PLTRST), // TIME_SYNC1
// B24 configured in bootblock
PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL), // X1_SLOT_LAN_WAKE_N
/* GPIO Community C */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // DRAM_HSCL_1P0
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // DRAM_HSDA_1P0
PAD_CFG_GPI_SCI_LOW(GPP_C02, NONE, DEEP, LEVEL), // PCA9555_0_INT_N
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), // SML0_SCL_LAN_PCIE
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), // SML0_SDA_LAN_PCIE
PAD_CFG_GPO(GPP_C05, 0, DEEP), // CRD1_PWREN
PAD_NC(GPP_C06, NONE), // N/C
PAD_NC(GPP_C07, NONE), // N/C
PAD_CFG_GPO(GPP_C08, 0, DEEP), // CRD2_PWREN
/* Source Clock Requests */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), // SRCCLKREQ0: X8_GEN5_DT_CEM_SLOT_FOR_DGFX
PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // SRCCLKREQ1: X4_GEN5_DT_CEM_SLOT
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), // SRCCLKREQ2: X1_GEN4_DT_CEM_SLOT
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // SRCCLKREQ3: I226_LAN
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), // SRCCLKREQ4: M.2_WLAN_KEY-E
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), // SRCCLKREQ5: M.2_WWAN_KEY-B
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SRCCLKREQ6: X4_GEN4_M.2_SSD_KEY-M
PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SRCCLKREQ7: N/C, exposed on RFSH
PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), // SRCCLKREQ8: N/C, exposed on RFSH
PAD_CFG_GPO(GPP_C15, 1, PLTRST), // CAM1_CLK_EN
/* Thunderbolt/USB-C Display Data Channels */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // TBT_LSX1_TXD
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // TBT_LSX1_RXD
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // MOD_TCSS1_LS_TX_DDC_SCL
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // MOD_TCSS1_LS_RX_DDC_SDA
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), // MOD_TCSS2_LS_TX_DDC_SCL
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), // MOD_TCSS2_LS_RX_DDC_SDA
/* GPIO Community D */
PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), // IMGCLKOUT_1
PAD_CFG_GPO(GPP_D01, 1, DEEP), // MOD_TCSS1_TYP_A_VBUS_EN
PAD_CFG_GPO(GPP_D02, 1, DEEP), // VBY1_BKLTEN_3P3V
PAD_CFG_GPO(GPP_D03, 1, PLTRST), // M.2_WWAN_PERST_GPIO_N
PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), // IMGCLKOUT_0
PAD_NC(GPP_D05, NONE), // Unknown, exposed on RFSH
PAD_NC(GPP_D06, NONE), // Unknown, exposed on RFSH
PAD_NC(GPP_D07, NONE), // N/C
PAD_NC(GPP_D08, NONE), // N/C
PAD_CFG_GPO(GPP_D09, 1, PLTRST), // PEG_SLOT_RST_N
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BCLK_I2S0_SCLK_HDR
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), // HDA_SYNC_I2S0_SFRM_HDR
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), // HDA_SDO_I2S0_TXD_HDR
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), // HDA_SDI0_I2S0_RXD_HDR
PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI), // COINLESS_MODE_SELECT
PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG), // SPI_TPM_INT_N
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), // HDA_RST_N_HDR
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_SDI1_HDR
PAD_CFG_GPO(GPP_D19, 1, PLTRST), // X1_DT_PCIE_RST_N
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), // PD_TCP1_DBG_I3C_SDA
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), // PD_TCP1_DBG_I3C_SCL
PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL), // PEG_SLOT_WAKE_N
PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL), // X4_SLOT_WAKE_N
/* GPIO Community E */
PAD_CFG_GPO(GPP_E01, 0, PLTRST), // CRD2_RST_N
PAD_NC(GPP_E02, NONE), // N/C
PAD_CFG_GPO(GPP_E03, 1, PLTRST), // X4_DT_PCIE_RST_N
PAD_CFG_GPI_SCI_LOW(GPP_E05, NONE, DEEP, LEVEL), // VBY1_INT_3P3V_N
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), // SECURE_CAM_SW
PAD_CFG_NF(GPP_E07, NONE, DEEP, NF1), // DDPA_DDIA_CTRLCLK_R
PAD_CFG_NF(GPP_E08, NONE, DEEP, NF1), // DDPA_DDIA_CTRLDATA_R
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), // USB32_TYPEA_CONN1_OC0_N
PAD_CFG_GPO(GPP_E10, 0, PLTRST), // CAM1_RST_N
PAD_NC(GPP_E11, NONE), // GSPI0_CLK: N/C, exposed on RFSH
PAD_NC(GPP_E12, NONE), // GSPI0_MOSI: N/C, exposed on RFSH
PAD_NC(GPP_E13, NONE), // GSPI0_MISO: N/C, exposed on RFSH
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), // PD_ALERT_N
PAD_NC(GPP_E15, NONE), // N/C
PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), // DEV_MODE_ID
PAD_NC(GPP_E17, NONE), // GSPI0_CS0: N/C, exposed on RFSH
PAD_NC(GPP_E18, NONE), // N/C, TP1506
PAD_NC(GPP_E19, NONE), // X8_PEG_SEL_PROCHOT_N
PAD_NC(GPP_E20, NONE), // X8_PEG_DGPU_PWR_OK_3P3
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), // PMC_ALERT_N
PAD_NC(GPP_E22, NONE), // N/C
/* GPIO Community F */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), // CNV_RF_RESET_R_N
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), // CRF_CLKREQ_R
PAD_NC(GPP_F06, NONE), // N/C
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), // IMGCLKOUT_2
PAD_CFG_GPO(GPP_F08, 0, PLTRST), // N/C, but exposed on FUSA and J25
PAD_CFG_NF(GPP_F09, NONE, DEEP, NF4), // ISH_INT_GP11_CVS_+V12S_CRD1
PAD_CFG_GPO(GPP_F10, 0, PLTRST), // PEG_SLOT_PWR_EN_N
PAD_CFG_GPO(GPP_F11, 1, DEEP), // MOD_TCSS2_TYP_A_VBUS_EN
PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, PLTRST, LEVEL, ACPI), // MOD_TCSS2_DETECT
PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, LEVEL, ACPI), // MOD_TCSS2_DETECT_R
PAD_NC(GPP_F14, NONE), // N/C
PAD_NC(GPP_F15, NONE), // N/C
PAD_NC(GPP_F16, NONE), // N/C
PAD_CFG_GPI(GPP_F17, NONE, DEEP), // CODEC_IRQ_HDR
PAD_NC(GPP_F18, NONE), // N/C
PAD_CFG_GPO(GPP_F19, 0, PLTRST), // PRIVACY_LED_CAM2
PAD_CFG_GPO(GPP_F20, 0, PLTRST), // PRIVACY_LED_CAM1_CVS_HST_WAKE
PAD_CFG_GPO(GPP_F22, 1, PLTRST), // MOD_TCSS1/2_SX_CNTRL_R
PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL), // M.2_WWAN_WAKE
/* GPIO Community H */
PAD_CFG_GPO(GPP_H00, 0, PLTRST), // CAM2_CLK_EN
PAD_CFG_GPO(GPP_H01, 0, PLTRST), // CAM2_FLSH_STROBE
PAD_CFG_GPO(GPP_H02, 0, PLTRST), // DNX_IN_PROG_LED_R
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), // MIC_MUTE
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1), // I2C2_SDA_CAM_FLSH
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1), // I2C2_SCL_CAM_FLSH
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA_AUDIO_HDR
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL_AUDIO_HDR
/* GPP_H08, H09, H10 and H11 are configured in bootblock for early UART0 bringup
* GPP_H14 and H15 are configured in bootblock for early UART1 bringup */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), // CPU_C10_GATE_N
PAD_NC(GPP_H16, NONE), // N/C
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // MIC_MUTE_LED
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C0_SDA_PORT80_DISP_R
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C0_SCL_PORT80_DISP_R
PAD_NC(GPP_H21, NONE), // N/C
PAD_NC(GPP_H22, NONE), // N/C
/* GPIO Community S (SoundWire) */
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), // SNDW3_CLK_CODEC
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), // SNDW3_DATA0_CODEC
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), // SNDW3_DATA1_CODEC
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), // SNDW3_DATA2_CODEC
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2), // SNDW2_CLK_DMIC_CLK_A
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2), // SNDW2_DATA0
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), // SNDW1_CLK_DMIC1
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), // SNDW1_DATA0_DMIC1
/* GPIO Community V */
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // BATLOW_N
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LANWAKE_N
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PM_PWRBTN_N
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // PM_SLP_S3_N
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), // PM_SLP_S4_N
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), // PM_SLP_A_N
PAD_NC(GPP_V07, NONE), // N/C
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), // SLP_WLAN_N
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // PM_SLP_S5_N
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), // LAN_PHY_PC
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LAN_SW_EN
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), // WAKE_N
PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), // H_CATERR_N
PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // FORCE_PROCHOT
PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), // THERMTRIP_N
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), // VCCST_EN_R
PAD_CFG_GPO(GPP_V17, 1, DEEP), // MOD_TCSS1_RT_S0IX_ENTRY_EXIT_N
};

12
src/mainboard/intel/pantherlake_crb/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
// TODO: Realtek ALC722-CG pins
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;

20
src/mainboard/intel/pantherlake_crb/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include "gpio.h"
static void init_mainboard(void *chip_info)
{
gpio_configure_pads(main_gpio_table, ARRAY_SIZE(main_gpio_table));
}
struct chip_operations mainboard_ops = {
.init = init_mainboard,
};
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->PchLegacyIoLowLatency = 1;
}

64
src/mainboard/intel/pantherlake_crb/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
static const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR5,
.user_bd = BOARD_TYPE_ULT_ULX,
.ect = true,
.rcomp = {
.resistor = 100,
},
.ddr_config = {
.dq_pins_interleaved = false,
}
};
static const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = {
.addr_dimm[0] = 0x50,
.addr_dimm[1] = 0x0,
},
[1] = {
.addr_dimm[0] = 0x50,
.addr_dimm[1] = 0x0,
},
[2] = {
.addr_dimm[0] = 0x52,
.addr_dimm[1] = 0x0,
},
[3] = {
.addr_dimm[0] = 0x52,
.addr_dimm[1] = 0x0,
},
},
};
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const uint8_t channel_to_ckd_qck[] = { 0, 0, 1, 0, 0, 0, 1, 0 };
memcpy(mupd->FspmConfig.ChannelToCkdQckMapping,
channel_to_ckd_qck, sizeof(channel_to_ckd_qck));
const uint8_t phy_clock_to_ckd_dimm[] = { 0, 0, 0, 0, 8, 0, 8, 0 };
memcpy(mupd->FspmConfig.PhyClockToCkdDimm,
phy_clock_to_ckd_dimm, sizeof(phy_clock_to_ckd_dimm));
// Raise FSP loglevel for verbose debugging. Requires debug build (NDA).
// mupd->FspmConfig.PcdSerialDebugLevel = 4;
// GpioOverride needs to be disabled, messes with PCIe CLKREQs
mupd->FspmConfig.GpioOverride = 0;
mupd->FspmConfig.EnableAbove4GBMmio = 1;
memcfg_init(mupd, &mem_config, &spd_info, false);
}