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mb/google/fatcat/kinmen: Remove RTD3 config for SSD

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The Kinmen hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.

BUG=460038237
TEST=Build and boot to OS on Kinmen, verify SSD still functions
    correctly and power state transitions align with HW design.

Change-Id: I5e20c247bd45427f817e7afd8355a71c7a9c161c
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ivy Jian 2026-02-03 14:52:09 +08:00 • committed by Matt DeVillier
commit a6e77b1e64
1 changed files with 0 additions and 7 deletions
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7
src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
View file

@ -374,13 +374,6 @@ chip soc/intel/pantherlake
.clk_req = 1,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)"
register "srcclk_pin" = "1"
device generic 0 on end
end
end # Gen5 M.2 SSD
device ref cnvi_wifi on
chip drivers/wifi/generic