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mb/google/ocelot/var/ocicat: Remove RTD3 config for SSD

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The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree.

BUG=b:481143310
TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design.

Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
lai.kaiden 2026-02-03 14:03:34 +08:00 • committed by Matt DeVillier
commit 1777f962fd
1 changed files with 0 additions and 7 deletions
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7
src/mainboard/google/ocelot/variants/ocicat/overridetree.cb
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@ -365,13 +365,6 @@ chip soc/intel/pantherlake
.clk_req = 3,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)"
register "srcclk_pin" = "3"
device generic 0 on end
end
end # Gen4 M.2 SSD
device ref pcie_rp5 on