x86/mtrr: Avoid WC for VGA BARs above 4GiB

On Arrow Lake we ran out of variable MTRRs, leaving PCI BARs uncached.
This made the edk2 setup UI extremely slow due to UC MMIO/framebuffer
writes.

Ensure BAR ranges get a cacheable attribute instead of falling back to
UC.

Change-Id: I74a89cf334d1eb74bbfbb4b0f9621f098bfa4a89
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91109
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/x86/mtrr/mtrr.c

@@ -122,6 +122,16 @@ static int filter_vga_wrcomb(struct device *dev, struct resource *res)
 	if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
 		return 0;
 
+	/*
+	 * Only mark 32-bit BARs as WC. Some platforms expose additional large
+	 * prefetchable BARs above 4GiB for the iGPU, and tagging those as WC
+	 * can fragment the address space enough to exhaust variable MTRRs.
+	 * Keeping the below-4GiB framebuffer WC is the priority for payload UI
+	 * performance.
+	 */
+	if (res->size != 0 && res->base >= 0x100000000ULL)
+		return 0;
+
 	/* Add resource as write-combining in the address space. */
 	return 1;
 }