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mb/siemens/{mc_ehl2,mc_ehl5}: Fine-tune Gen1 TX Output De-Emphasis for PCIe RP #7

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On these two mainboards, a Gen1 device is connected on PCIe RP #7.
Measurements have shown that a value of -0.137 dB yields an optimal eye
TX mask test.

BUG=none
TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope

Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2026-01-27 10:21:22 +01:00 • committed by Werner Zeh
commit b117179256
2 changed files with 10 additions and 0 deletions
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5
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
View file

@ -62,6 +62,11 @@ chip soc/intel/elkhartlake
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[6]" = "true"
# Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB
register "pcie_mp_cfg[6]" = "{
.tx_gen1_de_emph = 0x3f,
}"
# Storage (SDCARD/EMMC) related UPDs
register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"

5
src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
View file

@ -62,6 +62,11 @@ chip soc/intel/elkhartlake
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[6]" = "true"
# Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB
register "pcie_mp_cfg[6]" = "{
.tx_gen1_de_emph = 0x3f,
}"
# Storage (SDCARD/EMMC) related UPDs
register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"