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mb/amd/birman_plus: Disable PCIe feature programming

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Before the PCIe features can be programmed FSP-S must set non
public bits in the EnumInitPhaseAfterPciEnumeration callback.
Violating this rule causes system instabilities and reboot loops,
depending on the selected features and hardware plugged into slots.

Since FSP-S can handle all types of PCIe features disable all of
them in coreboot and let FSP set the bits at the right time.

TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing
     system crashed.

Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2026-02-11 13:33:24 +01:00 • committed by Felix Held
commit 7493b41f37
1 changed files with 0 additions and 4 deletions
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4
src/mainboard/amd/birman_plus/Kconfig
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@ -8,10 +8,6 @@ config BOARD_AMD_BIRMANPLUS_COMMON
select DRIVERS_PCIE_RTD3_DEVICE
select DRIVERS_I2C_GENERIC
select MAINBOARD_HAS_CHROMEOS
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PCIEXP_L1_SUB_STATE
select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD
select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED
select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE