mb/google/nissa/var/riven: Support x32 memory configuration

Use GPP_E5 level to determine whether x32 memory configuration is
supported.

Schematic version: ZDKC-Proto_MB_20260209.pdf

BUG=b:337169542
TEST=Build and boot to OS. Verify functions work.

Change-Id: I51229e99242351d957cbe26a00d9c5440c5d6784
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91115
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/Kconfig

@@ -609,6 +609,7 @@ config BOARD_GOOGLE_RIVEN
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_INTEL_MIPI_CAMERA
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD

src/mainboard/google/brya/variants/riven/Makefile.mk

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

src/mainboard/google/brya/variants/riven/gpio.c

@@ -15,6 +15,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	/* D8  : SRCCLKREQ3# ==> NC */
 	PAD_NC(GPP_D8, NONE),
+	/* E5  : NC ==> GPP_E5_STRAP */
+	PAD_CFG_GPI_LOCK(GPP_E5, DN_20K, LOCK_CONFIG),
 	/* F12 : WWAN_RST_L */
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* H12 : UART0_RTS# ==> NC */
@@ -71,6 +73,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 	/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* E5  : NC ==> GPP_E5_STRAP */
+	PAD_CFG_GPI(GPP_E5, DN_20K, DEEP),
 };
 
 static const struct pad_config romstage_gpio_table[] = {

src/mainboard/google/brya/variants/riven/memory.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E5 High -> One RAM Chip
+	 * GPP_E5 Low  -> Two RAM Chip
+	 */
+	if (gpio_get(GPP_E5)) {
+		/* Disable all other channels except first two on each controller */
+		printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory"
+		"channels except first two on each memory controller.\n");
+		return (BIT(2) | BIT(3));
+	}
+
+	return 0;
+}