mb/google/brask/var/kulnex: Switch memory to DDR5

Kulnex uses DDR5 SODIMM. Configure the board to support DDR5.

BUG=b:480035819
TEST=build pass

Change-Id: Idc2205318bc5c9db8a4a699764de247e6fa25e66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91069
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/kulnex/Makefile.mk

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c

src/mainboard/google/brya/variants/kulnex/memory.c

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &ddr5_mem_config;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+}