Support for the rex touchscreen panel was needed for the RVP to validate touchscreen functionality. The LPSS touchscreen is mapped to I2C bus 4 and the rex panel is mapped to address 0x10.
BUG=b:458429110
TEST=None
Change-Id: I99b2c7beaab63da1877995c655ff8eddf9c3a69f
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Align the MPinit code with other Intel CPU drivers and move the
microcode update on the BSP to pre_mp_init(). This also ensures that
the microcode is located in CBFS before the MTRRs are set up using
x86_setup_mtrrs_with_detect() which removes caching the SPI flash
MMIO area.
No functional change, thus untested.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I47573dde5d471c9654ea9f14bd24b2a7087dd6df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds initial support for Intel's Customer Reference Board for
Edge Platforms.
Tested working:
- Serial output (RS232/LPSS) on Micro-USB port
- Built-in DisplayPort (DDI-A, NOT AIC)
- Built-in GbE NIC
- M.2 Gen4 NVME
- M.2 Gen4 WiFi
- PCIe Gen4 x1
- PCIe Gen5 x4
- USB ports
- Booting into Linux from USB/NVME
Not implemented yet (lack of hardware, waiting for upstreaming):
- Audio
- Thunderbolt
- IPU Cameras
Unresolved issues, untested:
- Automatic fan control (Unobtainable IT8659E datasheet).
- System suspend (Unobtainable IT8659E datasheet).
- PCIe Gen5 x8 (Likely an issue with early silicon sample).
For more information please refer to #854345 (Intel CNDA).
Change-Id: I1d4e4dd4d18f49bd72405275fc96b7ca0630f612
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree.
BUG=b:481143310
TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design.
Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The Matsu hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=443612246
TEST=Build and boot to OS on Matsu, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I84db81c17afffafbdb6c7abcc752009c824bc2ed
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91086
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The Kinmen hardware design does not have a power load switch for
the SSD. Without it, the platform cannot cut off the main power rail
to the device to enter D3cold.
Therefore, remove the RTD3 chip driver and its associated GPIO
configurations (enable/reset) in the overridetree to align with the
hardware capability. The system will support D3hot instead of D3cold.
BUG=460038237
TEST=Build and boot to OS on Kinmen, verify SSD still functions
correctly and power state transitions align with HW design.
Change-Id: I5e20c247bd45427f817e7afd8355a71c7a9c161c
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for BWMYAX32P8A-32G
DRAM Part Name ID to assign
BWMYAX32P8A-32G 3 (0011)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I4b26b3c74c2985d9b663bc8eb72824d1ca82850b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91052
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Update SaGv work point 4 frequency value as per recommendation
from power and performance team.
BUG=b:461762075
TEST=Boot to OS on fatcat board, verified performance improvements
and frequency setting.
Change-Id: Ic4dfe6bf5a441b491a27e952010a43d4f7a68af5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add all known PCI bridge devices to the DSDT. This allows to reference
the devices from DSDT, allowing to add more SoC DSDT code and it allows
mainboard developers to add board specific ACPI code for devices behind
PCIe bridges (like NVMe D3cold).
Currently this is only possible using SSDT generators. The SSDT ACPI
generation is also broken, since the mainboard SSDT is run before SoC
SSDT, causing the interpreter to complain about missing devices.
TEST=Still boots on amd/birman_plus. No ACPI errors seen in dmesg.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I9d6f84b97fa943bb531d6b7b3f16c0422cd7901f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89456
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load microcode from CBFS before setting up MTRRs using
x86_setup_mtrrs_with_detect(), since it will remove caching the
SPI flash MMIO area and thus slow down CBFS accesses.
TEST=Booted on AMD/crater with CBFS_VERIFICATION enabled. The system
boots 6msec faster than before.
Change-Id: I3fafb98c1348daa549448707db88954316a12ff2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change introduces a check to ensure Power Delivery (PD)
negotiation is enabled when the device is in a specific vboot state.
PD negotiation will now be enabled if:
1. It is explicitly required by the hardware sync logic.
2. The device is in Developer Mode.
3. The device is in Recovery Mode.
4. A recovery request is pending.
This ensures that charging and PD sync are prioritized during
critical recovery and development paths.
This patch ensures the factory process remains powered by enabling
early charging based on the specific vboot mode.
In normal user scenarios, early charging is bypassed to allow higher
-level software to manage power negotiation according to standard
policy.
BUG=b:481546101
TEST=Build and boot on google/quartz. Verified PD negotiation is
active in developer/recovery mode.
Change-Id: I44b2ebd4fe3eec78a6df235df6282264dd97341f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91096
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The current bmp_logo_filename implementation returns static filenames
based on Kconfig or ChromeOS branding levels. This lacks flexibility
for boards that need to select a logo dynamically at runtime (e.g.,
based on SKU ID or hardware straps).
Introduce a weak function mainboard_bmp_logo_filename() that can be
overridden by mainboard code. If the mainboard implementation returns
a non-NULL string, that filename is used; otherwise, the logic falls
back to the existing default behavior.
BUG=None
BRANCH=None
TEST=Verified that a mainboard can override the logo filename by
implementing mainboard_bmp_logo_filename. Verified default behavior
is preserved when no override is present.
Change-Id: Ia410dfb2a7a88779bb8eb4551605747bb326d353
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91082
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
waddledee dosn't have a MIPI camera, so drop the unused ipu devicetree
reference.
Change-Id: Ieca23f03d83fe1feeb026a923aec2c5fab6a9fe5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
- Add IPUA device under igpu (gfx/generic) for variants with IPU:
bugzzy, drawcia, haboki, lalala, magolor, storo, waddledoo
- Set ssdb.link_used to match cio2_prt
- Drop ssdb.rom_type and rom_address from mipi_camera sensor nodes;
JSL doesn't use this, and it causes a BSOD under Windows
- Add missing sensor_name for CAMERA_SENSOR on magolor and waddledoo
TEST=build/boot Win11 on magolor, verify MIPI camera functional
Change-Id: I7fca3c6bb8bca9271a4dbaf888cc28304d6545a8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91066
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For dedede laptops, switch from using GMA_DEFAULT_PANEL(0), previously
set in the baseboard, to using a per-variant gfx generic chip driver,
so that variants which use IPU/MIPI cameras can add the IPUA camera
device in a subsequent commit.
For dedede laptops, this is a no-op; for Chromeboxes, it removes the
previously defined internal panel which they do not have.
TEST=build/boot dexi, magolor variants. verify ACPI brightness controls
still functional under Linux and Windows for the latter.
Change-Id: I83fd2d952ca785bef8210024cbbb9280688d6a5e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
JSL was missing an entry for the IGD, preventing the use of
DRIVERS_GFX_GENERIC since the call to acpi_device_scope() for it
returned null. Add the missing IGD entry, consistent with other
modern Intel SoCs.
TEST=build/boot google/magolor with chip drivers/gfx/generic entry
and verify SSDT entry correctly created.
Change-Id: Idf1d8992b45c60f68fd2b156c6e7cae816df84b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
According to Intel SA Doc#873795, select HAVE_CHIPSETINIT_BINARY
on nissa and trulo baseboard.
BUG=b:447290550
TEST=1. build coreboot
2. check log to confirm load chipsetinit.bin successfully.
Change-Id: I66a0c1a3dbfbbf563461b319c5839910dfc11656
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90698
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kao, Ben <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gpio-keys is a Linux-specific ACPI interface, and the kernel driver
does not care what the status is. Windows does not have drivers
however, so set the ACPI status to HIDDEN to avoid an unknown device
from appearing in Device Manager.
TEST=build/boot Win11 on google/magolor, verify PENH device no longer
listed under Device Manager.
Change-Id: I8a476e57b36c26795bfe9605e725ba3d5f860b3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91068
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements the recommended BIOS power delivery settings
described in Intel WW03 2026 Wildcat Lake platform message of the
week (844458).
Key changes:
- Enable acoustic noise mitigation with SLEW_FAST_4 for GT domain
- Enable fast package C-state ramp disable for GT domain
- Update fast_vmode_i_trip to 25A (was 38A)
- Enable GT VR fast voltage mode and CEP
BUG=b:467349691
TEST=Build ocelot and verify that the system boots to UI with the
updated parameters.
[SPEW ] IccMax[1]:0x90
[SPEW ] EnableFastVmode[1]:0x1
[SPEW ] IccLimit[1]:0x64
[SPEW ] CepEnable[1]:0x1
[SPEW ] FastPkgCRampDisable[1]:0x1
[SPEW ] SlowSlewRate[1]:0x1
[SPEW ] AcousticNoiseMitigation:0x1
Change-Id: I76cefc79457c6bcfb250ba3525c501a126b526fb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Improving the driving capabilities of USB2 enables the eye
diagram of a USB camera to pass the test.
BUG=b:478790360
TEST=emerge-fatcat coreboot, EA test pass
Change-Id: Id400fb541fd1c797ea602e3f8e12be07ed05b5b8
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91047
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add TG-XTI05101 MIPI panel for Wugtrio.
Datasheet:TG-XTI05101-01A-SPEC-V1_20260202.pdf
BUG=b:479758139
TEST=emerge-staryu coreboot depthcharge libpayload chromeos-bootimage
can see the fw screen,jump to kernel and can see chromeos logo
BRANCH=corsola
Change-Id: Ibec69165fe39675d6e6ef4e0db7733825af7bf56
Signed-off-by: Cindy Lu <luyi8@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90873
Reviewed-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use I2C block read command to access the VPD EEPROM to speed up
SMBIOS table generation, but keep the single byte read as fallback.
Shrink the size of the mainboard version string to not crossing the
128 byte block boundary.
TEST=On Lenovo X220 the BS_WRITE_TABLES is 15 msec faster.
Change-Id: Ida21a8dc653551440e79b062abcce9194d11bef4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91029
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ensure that the mainboard version string is fully contained within
one 128byte block of the EEPROM. Since it's read from offset 0x27
it can be 89 characters long. One byte for the final null terminator.
Change-Id: I264ea2d1f634bb3493858da9f066bd6cef1ca960
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Expose the existing i2c block read functionality usually used in
romstage to the smbus_bus_operations for use in ramstage.
This allows faster reading of I2C EEPROM in ramstage.
TEST=Can read I2C EEPROM on Lenovo X220 using I2C block read.
Change-Id: I1264f17317c3095f9661b0ab6aa3124a00ce86c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91028
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Simplify Wildcat Lake SKU configuration by consolidating multiple
SKU variants into a single WCL_SKU_1 configuration. All WCL device
IDs (WCL_ID_2 through WCL_ID_5) now map to WCL_SKU_1 instead of
having separate SKU definitions.
Additionally, update GT domain VR controller settings for WCL_SKU_1:
- Set IccMax to 36A (144 in register units) for GT domain
BUG=b:467349691
TEST=Build ocelot and verify system boots with consolidated WCL SKU
configuration. Confirm GT VR IccMax is set to 36A in coreboot logs.
Change-Id: I6466c150bcd712430cf2595db5be13039688fecb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refine the critically low battery alert logic to only trigger when the
lid is closed. This prevents the red LED alert from firing
unnecessarily when the system is open, or ensures it specifically
targets the user notification flow designed for a closed-lid blocked
boot.
This change requires VBOOT_LID_SWITCH to be enabled to correctly
detect the lid state in romstage.
BUG=none
TEST=Verify LED behavior on Google/Quartz with low battery and AC unplugged.
Change-Id: Ibe9e7b3bd46527f72a873f161cc359e0641c35f4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
If the system is powered on while the lid is closed (e.g., via a
power button or auto-power-on event), there is no need to initialize
the internal display.
Update display_startup() to check the lid state via get_lid_switch().
Skipping initialization in this state reduces unnecessary power
consumption and slightly improves boot time for closed-lid scenarios.
BUG=none
TEST=Verify display does not initialize when lid is closed on
Google/Quartz.
Change-Id: I2ec48876f102b7309a1401aa9d7bdc0fdc96791a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91011
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the ChromeEC driver now supporting lid state retrieval via host
commands for non-LPC platforms, enable VBOOT_LID_SWITCH for Bluey.
This allows the mainboard to utilize vboot features that depend on
the lid status, such as preventing boot when the lid is closed.
BUG=none
TEST=Verify LID status on Google/Quartz.
Change-Id: Idfc45258170e86a673aede9fc63a87a9a2ca3c3b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91009
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On non-LPC platforms (such as those using I2C or SPI for EC comms),
the EC memory map is not directly accessible via memory-mapped I/O.
Instead, these platforms must use the EC_CMD_READ_MEMMAP host command
to retrieve system information.
Implement google_chromeec_get_switches() using this host command for
non-LPC systems. This enables get_lid_switch() to function correctly
on eSPI-based and other non-LPC mainboards, allowing them to support
lid-controlled logic.
BUG=none
TEST=Verify the LID state using get_lid_switch() on Google/Quartz.
Change-Id: Ic7dbe1bcf6b528dfefc168e2f0de0357430dc84d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct the GPP_V17 gpio pin from platform reset to deep to
avoid uncontrollable behavior in s0ix mode.
BUG=b:475990377
BRANCH=none
TEST=Build and boot to OS, check GPP_V17 behavior is correct.
Change-Id: I8f8bc59b71b8f8b4c5d4dbdbdcf8fcbfdbd96921
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91050
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:452180266
BRANCH=none
TEST=Build and check system can boot to OS
Change-Id: I6092f620f4ae0635ffbbd9c26cf0ce0d55b44ba8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Increase the maximum root port count for Panther Lake (PTL) to 12.
While the actual number of active ports may vary depending on the
specific SKU and strapping, setting this constant to 12 is safe
and systematically handled by the existing SoC logic.
Systematic Bounds: The common PCIe root port driver (pcie_rp.c)
and PTL-specific FSP parameter logic utilize ptl_rp_groups and
PCI configuration space accesses to determine the actual hardware
limits at runtime.
Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper
bound for array allocations and iteration loops. Setting this to
12 accommodates the maximum possible PTL configuration without
over-allocating resources.
Consistency: This aligns the configuration with the hardware's
maximum capability, allowing the silicon initialization code to
dynamically "fill in" the details for lower-port SKUs without
requiring further Kconfig changes.
BUG=None
TEST=Able to build boards that use different PTL SKUs.
Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 261274992d.
Reason for revert: Panther Lake U/H Processor EDS vol 1/2 says PTL-U/H
12Xe has 12 PCIe RPs where else PTL-H 4Xe has 10 PCIe RPs.
This change has limit the capability for devices that is build with
PTL-U/H 12Xe hence, we are seeing below errors
```
[ERROR] pcie_rp_update_devicetree: Error: Group exceeds
CONFIG_MAX_ROOT_PORTS.
```
As a result PCIe Gen 5 devices (SSD) unable to init and enabled during
boot.
Change-Id: I0443554ef8f619c485f16edc576794f9cf2e85ea
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91075
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit dec1dfe160.
Reason for revert: It is causing ADSP load failure in the OS.
BUG=b:480195888
TEST=Able to load the ADSP on Google/Quenbi.
Change-Id: I029c2b7ba74764a15227e44edc3be755cb8b9363
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91072
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
configure_tdp() selects the power limit table based on the
SA PCI device ID and the CPU's nominal TDP.
Add a 45W entry for PCI_DID_INTEL_ARL_H_ID_1 (e.g. Intel
285H) so power limits are programmed instead of being
skipped.
Change-Id: Ia90633b43b78bc616ff0b750ed3ef44333019957
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91056
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 4a09db75d9 ("util/autoport: Add
support for 9 Series PCHs (Lynx Point Refresh)") got submitted after
commit 01d82febb2 ("util/autoport:
Separate handling of Kconfig selects").
The latter commit was specifically made so that the former commit could
properly express a Kconfig select with a condition. However, the former
commit did not get updated, and got submitted as-is since there was no
unresolved review comment to keep track of this TODO. As a result, what
should have been a conditional Kconfig select but with the condition in
a comment to work around limitations of the original system accidentally
became a bool option override.
So, simply use the new system to express a conditional Kconfig select.
This fixes the wrongly-generated Kconfig as well as the original issue.
Even though this would still have worked, the `USE_BROADWELL_MRC` option
must be selected for boards with a Lynx Point Refresh PCH, since Haswell
MRC will not work on those PCHs. Still, this can be caught and corrected
during review, in case any board ports are made before this fix lands.
Change-Id: I98f032283e9e5bb5ec13dbff382304b7abfec07e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91027
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Bump the submodule and thus include the following new commits:
hw-gfx-gma-i2c: Reduce EDID I2C timeout
transcoder: Don't try to disable disabled DDI func
gfxtest: Handle 64-bit aperture base and register location
gma: Get DPCD 1.1+ displays out of D3
gma: Work around GNATprove issue with nested loops
TEST=libgfxinit still works on Lenovo X220 and is 450msec faster.
Change-Id: If32fd0256280ee8539c6bbc0440c30d89711996c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91030
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently not all fixed MMIO ranges are advertised to the resource
allocator. This is not an issue as long bottom-up allocation is
used and as long as only small PCI BARs are present on the system.
Tell the PCI resource allocator about active MCH BARs to not overlap
PCI BARs with MCH BARs.
TEST=Can still boot on Lenovo X220. No issues seen in coreboot or Linux.
Change-Id: I9148ce492b3b16542bae2737c98b0e6fd0701745
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Handle ADL-P and ADL-M PCI IDs the same as ADL-N and RPL-P for
dumping LPC registers. Add southbridge names/labels for ADL-P
and ADL-M.
TEST=build and run 'inteltool -l' to dump LPC/eSPI registers on
google/taeko (RPL-P), verify output matches LPC decode set in devicetree
Change-Id: I84901a8e25eb679acb31be1caa8fffa667454c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a follow-up patch (CB:90962), the list will be changed to a circular
one, and list_node fields 'next' and 'prev' will become private to the
implementation.
To allow smooth transition to circular lists for all call sites, add the
following functions to the list API:
- list_is_empty()
- list_next()
- list_prev()
- list_first()
- list_last()
- list_length()
All list API call sites are expected to use the public API instead of
the raw 'next' and 'prev' pointers.
Change-Id: Ib1040f5caab8550ea52db9b55a074d7d79c591e5
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The code was copied from newer generation SoC supporting parallel
SMM relocation, but it wasn't properly cleaned.
Gen1 doesn't support parallel SMM relocation, so fix the comments.
Change-Id: Idbe6d2c18f668a9c1922b93ce1b2cc3d126ff2f9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91013
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
66 | #define INT32_MAX ((int32_t)0x7FFFFFFF)
| ^~~~~~~~~
[...]
129 | #define INT32_MAX (0x7FFFFFFF)
| ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```
Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.
Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
