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util/autoport: Separate handling of Kconfig selects

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Previously, `KconfigBool` was used to generate selects (if the option
value is true) or bool option overrides (if the option value is false).
This approach is not particularly flexible: one cannot have conditions
for selects, and bool option overrides can only disable options.

Introduce a new `KconfigStatement` map of Kconfig names to conditions.
An empty condition string means that no condition is to be added. Also
update uses of `KconfigBool` to `KconfigSelect` to preserve autoport's
current behaviour.

TEST=Generated files for HP ProBook 4740s (Sandy Bridge) do not change.

Change-Id: I88666ce0d761c1d393ac602196229ec0878fed42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Angel Pons 2025-12-21 20:03:36 +01:00 • committed by Matt DeVillier
commit 01d82febb2
9 changed files with 39 additions and 33 deletions
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2
util/autoport/azalia.go
View file

@ -11,7 +11,7 @@ type azalia struct {
func (i azalia) Scan(ctx Context, addr PCIDevData) {
/* FIXME: Rework to output new verb table format, or better
yet use hda-decoder to avoid duplicating functionality */
KconfigBool["AZALIA_USE_LEGACY_VERB_TABLE"] = true
KconfigSelect["AZALIA_USE_LEGACY_VERB_TABLE"] = ""
az := Create(ctx, "hda_verb.c")
defer az.Close()

4
util/autoport/bd82x6x.go
View file

@ -62,8 +62,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
inteltool := ctx.InfoSource.GetInteltool()
GPIO(ctx, inteltool)
KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true
KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
KconfigSelect["SOUTHBRIDGE_INTEL_"+b.variant] = ""
KconfigSelect["SERIRQ_CONTINUOUS_MODE"] = ""
KconfigInt["USBDEBUG_HCD_INDEX"] = 2
KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this"
dmi := ctx.InfoSource.GetDMI()

2
util/autoport/ec_fixme.go
View file

@ -60,7 +60,7 @@ Method(_PTS,1)
}
`
KconfigBool["EC_ACPI"] = true
KconfigSelect["EC_ACPI"] = ""
si := Create(ctx, "acpi/superio.asl")
defer si.Close()

4
util/autoport/ec_lenovo.go
View file

@ -149,8 +149,8 @@ void mainboard_smi_sleep(u8 slp_typ)
Add_SPDX(ec, ASL, GPL2_only)
ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n")
KconfigBool["EC_LENOVO_PMH7"] = true
KconfigBool["EC_LENOVO_H8"] = true
KconfigSelect["EC_LENOVO_PMH7"] = ""
KconfigSelect["EC_LENOVO_H8"] = ""
pmh := DevTreeNode{
Chip: "ec/lenovo/pmh7",

6
util/autoport/haswell.go
View file

@ -101,9 +101,9 @@ func (i haswellmc) Scan(ctx Context, addr PCIDevData) {
PutPCIDev(addr, "Host bridge")
KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true
KconfigSelect["NORTHBRIDGE_INTEL_HASWELL"] = ""
KconfigSelect["HAVE_ACPI_TABLES"] = ""
KconfigSelect["HAVE_ACPI_RESUME"] = ""
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
File: "cpu/intel/common/acpi/cpu.asl",

6
util/autoport/lynxpoint.go
View file

@ -143,11 +143,11 @@ func (b lynxpoint) Scan(ctx Context, addr PCIDevData) {
GPIO(ctx, inteltool)
}
KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true
KconfigSelect["SOUTHBRIDGE_INTEL_LYNXPOINT"] = ""
if isULT {
KconfigBool["INTEL_LYNXPOINT_LP"] = true
KconfigSelect["INTEL_LYNXPOINT_LP"] = ""
}
KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true
KconfigSelect["SERIRQ_CONTINUOUS_MODE"] = ""
if isULT {
KconfigInt["USBDEBUG_HCD_INDEX"] = 1
} else {

36
util/autoport/main.go
View file

@ -130,6 +130,7 @@ var KconfigComment map[string]string = map[string]string{}
var KconfigString map[string]string = map[string]string{}
var KconfigHex map[string]uint32 = map[string]uint32{}
var KconfigInt map[string]int = map[string]int{}
var KconfigSelect map[string]string = map[string]string{}
var ROMSizeKB = 0
var ROMProtocol = ""
var FlashROMSupport = ""
@ -572,6 +573,14 @@ func makeComment(name string) string {
return " # " + cmt
}
func makeSelect(name string) string {
condition, ok := KconfigSelect[name]
if !ok || condition == "" {
return name + makeComment(name)
}
return name + " if " + condition + makeComment(name)
}
func makeKconfig(ctx Context) {
kc := Create(ctx, "Kconfig")
defer kc.Close()
@ -581,33 +590,30 @@ func makeKconfig(ctx Context) {
fmt.Fprintf(kc, "config BOARD_SPECIFIC_OPTIONS\n\tdef_bool y\n")
keys := []string{}
for name, val := range KconfigBool {
if val {
keys = append(keys, name)
}
for name, _ := range KconfigSelect {
keys = append(keys, name)
}
sort.Strings(keys)
for _, name := range keys {
fmt.Fprintf(kc, "\tselect %s%s\n", name, makeComment(name))
fmt.Fprintf(kc, "\tselect %s\n", makeSelect(name))
}
keys = nil
for name, val := range KconfigBool {
if !val {
keys = append(keys, name)
}
for name, _ := range KconfigBool {
keys = append(keys, name)
}
sort.Strings(keys)
for _, name := range keys {
var mapper map[bool]rune = map[bool]rune{false: 'n', true: 'y'}
fmt.Fprintf(kc, `
config %s%s
bool
default n
`, name, makeComment(name))
default %c
`, name, makeComment(name), mapper[KconfigBool[name]])
}
keys = nil
@ -742,7 +748,7 @@ func main() {
}
if dmi.IsLaptop {
KconfigBool["SYSTEM_TYPE_LAPTOP"] = true
KconfigSelect["SYSTEM_TYPE_LAPTOP"] = ""
}
ctx.SaneVendor = sanitize(ctx.Vendor)
for {
@ -767,7 +773,7 @@ func main() {
ScanRoot(ctx)
if IGDEnabled {
KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true
KconfigSelect["MAINBOARD_HAS_LIBGFXINIT"] = ""
KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this"
AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT")
}
@ -851,10 +857,10 @@ func main() {
}
if ROMSizeKB == 0 {
KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
KconfigSelect["BOARD_ROMSIZE_KB_2048"] = ""
KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"
} else {
KconfigBool[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = true
KconfigSelect[fmt.Sprintf("BOARD_ROMSIZE_KB_%d", ROMSizeKB)] = ""
}
makeKconfig(ctx)

2
util/autoport/rce823.go
View file

@ -30,7 +30,7 @@ func (r rce823) Scan(ctx Context, addr PCIDevData) {
PutPCIChip(addr, cur)
}
PutPCIDev(addr, "Ricoh SD card reader")
KconfigBool["DRIVERS_RICOH_RCE822"] = true
KconfigSelect["DRIVERS_RICOH_RCE822"] = ""
}
func init() {

10
util/autoport/sandybridge.go
View file

@ -62,11 +62,11 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
PutPCIDev(addr, "")
/* FIXME:XX some configs are unsupported. */
KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
KconfigBool["USE_NATIVE_RAMINIT"] = true
KconfigBool["INTEL_INT15"] = true
KconfigBool["HAVE_ACPI_TABLES"] = true
KconfigBool["HAVE_ACPI_RESUME"] = true
KconfigSelect["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = ""
KconfigSelect["USE_NATIVE_RAMINIT"] = ""
KconfigSelect["INTEL_INT15"] = ""
KconfigSelect["HAVE_ACPI_TABLES"] = ""
KconfigSelect["HAVE_ACPI_RESUME"] = ""
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
File: "cpu/intel/common/acpi/cpu.asl",