This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.
TEST=Verify that ocelot builds without any error
Change-Id: I8ba76d77764d4b9cec22c79b977ad9e486ae804e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88937
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fw_config
This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Ocelot mainboard variant. This overrides the default weak HDA
common initialization.
Change-Id: I11f9d8ae00d1a3d7f03e068aa3980ecd98a47ecd
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88933
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on QEMU with ECC. Use mmap_helper to handle loading of compressed
ramstage. Bootblock fits in SEEPROM with both console and LZ4
romstage compression, but not with verbose CBFS debug messages.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I91c72c52849eb1e3fafe43390351537d04382e46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.
If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67067
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I found a space(' ') that was probably added unintentionally
in the cbmem_run_init_hooks().
So i deleted it to make the code cleaner.
P.S. It seems that clang-format can correct issues like it but
clang-format is unusable currently. See util/lint/check-style.
And this style issue of the code hasn't been corrected since 2015.
So i decided to correct it manually for now.
Change-Id: I788047d51c1f2586c3480efc4a31848e287c5894
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88325
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is cherry-picked from:
https://github.com/Dasharo/coreboot.git
Branch: protectli_vault_kbl/release
Original commit hash: b2b0a2bafbbe9be640f0fd0d02d85c81c90b796b
Then it was modified after code review, to:
* make it configurable
* remove code duplication
Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Change-Id: I1350df3407aaa9b1fdaf9383972fac3a708bea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88221
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At first glance the order of IOHCs seems peculiar. However, the
order is not random. Explain the reasoning of the IOHC order in the
comment.
Change-Id: Ic8e567d48a0f8d95ff9785cdd0c5489ea3016f1a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
When SOC_AMD_COMMON_BLOCK_PSP_SMI is enabled probe for the SPI
flash before actually servicing PSP SMI requests. This allows
to check the SPI flash status register in the following SMIs
if the flash is busy without needing to probe it first.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iff01d0ea46f1bd2c32dbf4c4f65f9851fdf024e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88436
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Since the PSP SMI can trigger any time, even when ring 0 uses the SPI
controller backup and restore the SPI MMIO space in SMM, making
sure to not corrupt ongoing SPI transfers in ring 0.
There's still the possibility of register clobbering when the SPI
controller was busy and became ready before the SMI handler could
check the status bit.
TEST: Booted on AMD glinda with CONSOLE_SERIAL enabled and observed
no boot failure.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaa5270d93d4934b2e7ebdf04151f1c0d9f57cfb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88435
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The busy check is only supported on Fam 17h Picasso and Raven Ridge.
On other platforms the register might not exist and the bits always
read as ones. This prevents the PSP SMI handler from accessing
the SPI flash.
TEST: Ensured that the code does not block on 1Ah platforms.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The correct value for the IO base is at 0x3000000, so set it. Otherwise,
I/O operations (e.g. inb(), outb(), etc.) won't work.
Change-Id: I5106fa95401de53e70f0859d27e07d2b8fde9ca0
Signed-off-by: Carlos López <carlos.lopez@openchip.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85675
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add support for limiting SATA interface speed through the FSP parameter
'SataSpeedLimit'. This is useful for mainboards with physical design
constraints that require operating at lower speeds than what the
controller and drives support.
The implementation adds a new chip config option that mainboards can
set in their devicetree to control this behavior.
Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TXT SINIT ACM checks the PEG bridge memory ranges whether they are
correctly assigned in the MMIO space. If the bridge is enabled but no
device is attached to it, coreboot will not assign any resources (if
hotplug is not enabled). When SINIT ACM checks the ranges, it fails
on prefetchable range check.
Hide the PEG devices if the bridge is not active. PCIe bridges should
generally be hidden if hotplug is not enabled and there is no
downstream device.
TEST=Perform successful measured launch of Xen with Intel TXT on Dell
OptiPlex 9010.
Change-Id: I0bd104ab416376e96102738f2e47c8ce041497a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Hook up to the USB ACPI driver and enable the generation of ACPI code
for enabled USB devices.
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83211
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
All USB ports are working \o/
Change-Id: I49aa8a245f656b8b6e47ce3a0e69899c052cf3f3
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88716
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
GNR-AP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/ap
GNR-SP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/sp
GNR mainboards will by default use public FSP bin and headers.
If needing to use site-local FSP bin and headers, apply below
settings in the defconfig (use beechnutcity CRB as example),
CONFIG_FSP_USE_REPO=n
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/
graniterapids/sp/"
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I88701316e21ec4737539294d17926aa0abe8c1fd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Hancockc <hancock.chang@mitaccomputing.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Schumi Chu
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Granite Rapids SoC has 2 SKUs, a.k.a. GNR-AP and GNR-SP, which
use different FSP headers/binaries. Add Kconfig items to support
these SKU types.
Change-Id: Ie3a2d603f0a2c303e8f3c0911598742fbc25d73a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88897
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-by: Schumi Chu
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces changes to support the OCELOT4ES variant by
adding a conditional check in the EC header file for enabling this
new variant.
TEST=Verify that ocelot builds without any error
Change-Id: Id7b27ce405df8e67675834a069133c87af71fd37
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch unifies all the ocelot variants based on
`BOARD_GOOGLE_MODEL_OCELOT` to use the same mainboard part number
`Ocelot` for code cleanliness.
TEST=Verify that ocelot builds without any error
Change-Id: I461a8142b93b10200b28bfe8855363ce2a30051d
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88939
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the explicit `logo_valignment` setting from the
`common_soc_config` for Ocelot.
The default vertical alignment for the splash screen logo is
`FW_SPLASH_VALIGNMENT_CENTER`, which is the desired behavior for ocelot.
Change-Id: I967c6f0b6926d23a399d01197dbed9e40b979aff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Enable the i210 driver for this variant which uses I210 MACPHYs.
Additionally, add a function to retrieve a valid MAC Address for the
given MACPHY.
Change-Id: If519194f52910e4ace59095a997bafff7eab44ca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Configure SPI according to the mainboard wiring. Disable GSPI completely
as it is unused on this platform. Enable FSPI and configure it to
interface with the TPM device.
Implement TPM measured boot functionality starting from bootblock to
ensure secure boot chain validation from the earliest boot stage.
Change-Id: I89b60101c94393816b51154459f39bb22d5b976d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Enable UART0, UART1 and UART2 in the devicetree. Adjust current UART
console configuration from UART0 to UART2. Additionally, enable LPSS
UART for the coreboot console on UART2.
Change-Id: I4ba521b3edd6a37f726a256a26051d5ab9acadfc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88885
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A variant specific Kconfig file is introduced. This improves
configuration management by separating variant-specific options from the
baseboard.
Change-Id: I3760bf0ec2d16722ba99459244968ef2db249453
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Move the SOC-specific Kconfig options from the variant to the baseboard
configuration. This ensures all variants will inherit the correct SOC
selection.
This simplifies configuration and ensures consistency across variants.
Change-Id: Icf13ebd022dbe35f7c5deadfb425f1f9b572ed86
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
In total three USB ports are used:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
Overcurrent reporting is not supported for these ports.
Remove the appropriate UPDs in devicetree and move them to the
variant level to match the hardware configuration.
Change-Id: I9ab02780cfc11f88ddd2bb52bd7fbfb3fdd450ef
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard only uses I2C0 and I2C1. Disable all the others. Move I2C
configuration from baseboard to variant.
Change-Id: I0c554ea4da948bc96d6a392c39bcb07a25a79eb4
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88880
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard does not utilize CKLREQ signaling for PCIe. Only three
PCIe clock sources are used on this board. Configure the Root Ports
accordingly to hardware implementation.
Change-Id: If4241a05dd0c5df258d4a7018d71a21f7d314e69
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88879
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 and BE200 wifi sar table for pujjolo/pujjoquince
wifi sar config. Use fw_config to separate different wifi card settings.
WIFI_SAR_TABLE_PUJJOLO_AX211 :0
WIFI_SAR_TABLE_PUJJOLO_BE200 :1
WIFI_SAR_TABLE_PUJJOQUINCE_AX211 :2
option WIFI_SAR_TABLE_PUJJOQUINCE_BE200 :3
BUG=b:428071905
Test=emerge-nissa coreboot
Change-Id: Iea8b32a19c4c2116afb5e5e4014dbc32e484ae3e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add fivr related setting based on schematics 500E_S3A0_TWL_MB_FVT_20250527.pdf
BUG=b:437881361
TEST=Build and boot to OS, check suspend funtion work fine using
suspend_stress_test -c 5 command.
Change-Id: I6c7f2807cc6a9c7c82e28d26205b33d068792522
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the lapis variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:438785495
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_LAPIS
2. Run part_id_gen tool without any errors
Change-Id: Iabcc673a1868cea1d8a650af213d583cc2e27c28
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Increase the CBFS cache in the memory layout of MediaTek Chromebook SoCs
to allow larger payloads like LinuxBoot to be loaded correctly.
TEST=Build and boot coreboot with LinuxBoot payload for
Google/Cherry/Tomato.
Change-Id: I4ce15e04cc19612ef1eed0fa0674ef8a7fd21fbe
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Use i2c_eeprom_read() to speed up reading the SPD EEPROMs.
TEST=Booted on Lenovo X220 and used cbmem -t:
Before:
940:waiting for ME acknowledgment of raminit 116,514 (62,804)
After:
940:waiting for ME acknowledgment of raminit 110,212 (57,612)
Boots 5msec faster when MRC cache is present.
Change-Id: I500d7ff7a66b08b5036c0031e4fa20746d06df19
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Users have requested to be able to disable the power LED, so add
this as an option.
Change-Id: I74da148c7891ab3dd5e5b692239670c9937ab302
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88890
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Booted on Lenovo X220 and found the UEFI menu working.
Change-Id: I194ff7b663c092c90882de4e7408b4c1e907984e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use udelay() over reading port 80h to delay CPU operation.
Since SMBUS runs at 100Khz a typical operation takes about
200usec or more to complete. Using udelay(1) doesn't delay
the boot for too long.
TEST=Booted on Lenovo X220. No additional boot delay was found.
Change-Id: Ied745927b1c54b53d7450b8e0c0a03d648a3ebba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This should be 65W to match the standard 65W GaN chargers.
Change-Id: I9a2be32b3b377090694cf23c4a4b85db47108c48
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88784
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.
This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.
TEST=Builds successfully for x1p42100.
Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes a bug in load_and_render_logo_to_framebuffer where the
logo_bottom_margin was only correctly applied to the NORMAL
orientations.
For other orientations, the margin was incorrectly applied, resulting
in the logo not being positioned as expected.
TEST=Able to see logo footer in alignment with the logo center while
booting google/felino.
Change-Id: Ia886ef5305166b1307fcf5b0acd12582b4b6ad80
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
@0x1485e340
[INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
supported for secdata_kernel v0, return 0
[INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
forbidden
[INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
@0x1485e7c0
```
Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
