soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs

At first glance the order of IOHCs seems peculiar. However, the
order is not random. Explain the reasoning of the IOHC order in the
comment.

Change-Id: Ic8e567d48a0f8d95ff9785cdd0c5489ea3016f1a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>

src/soc/amd/genoa_poc/root_complex.c

@@ -4,6 +4,16 @@
 #include <amdblocks/root_complex.h>
 #include <types.h>
 
+/*
+ * The order of IOHCs here is not random. They are sorted so that:
+ * 1. The First IOHC is the one with primary FCH. We want the LPC/SMBUS
+ *    devices be on bus 0.
+ * 2. The rest of IOHCs are listed in an order so that ECAM MMIO region is one
+ *    continuous block for all domains.
+ *
+ * AGESA/OpenSIL sets up the PCI configuration decoding ranges in line with
+ * this.
+ */
 static const struct domain_iohc_info iohc_info[] = {
 	[0] = {
 		.fabric_id = 0x22,