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mb/google/bluey: Enable PMIC based slow charging in romstage

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Enable PMIC based slow charging in romstage until we have fast charging
solution enabled.

BUG=b:438004604
TEST=Verify battery charging during romstage.

Change-Id: Idb8ea7151a2a467194aee2b357d8a5f24e691717
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88928
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kapil Porwal 2025-08-25 09:44:44 +05:30 • committed by Subrata Banik
commit b67d88aecb
1 changed files with 25 additions and 0 deletions
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25
src/mainboard/google/bluey/romstage.c
View file

@ -5,9 +5,32 @@
#include <gpio.h>
#include <soc/aop_common.h>
#include <soc/qclib_common.h>
#include <soc/qcom_spmi.h>
#include <soc/shrm.h>
#include <soc/watchdog.h>
#define SMB1_SLAVE_ID 0x07
#define SMB2_SLAVE_ID 0x0A
#define SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG 0x2666
#define SMB1_CHGR_MAX_FCC_CFG ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
#define SMB2_CHGR_MAX_FCC_CFG ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_MAX_FAST_CHARGE_CURRENT_CFG)
#define SCHG_CHGR_CHARGING_ENABLE_CMD 0x2642
#define SMB1_CHGR_CHRG_EN_CMD ((SMB1_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
#define SMB2_CHGR_CHRG_EN_CMD ((SMB2_SLAVE_ID << 16) | SCHG_CHGR_CHARGING_ENABLE_CMD)
#define FCC_1A_STEP_50MA 0x14
#define CHRG_ENABLE 0x01
static void enable_battery_charging(void)
{
/* Configure FCC and enable charging */
printk(BIOS_INFO, "Use slow charging without fast charge support\n");
spmi_write8(SMB1_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
spmi_write8(SMB2_CHGR_MAX_FCC_CFG, FCC_1A_STEP_50MA);
spmi_write8(SMB1_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
spmi_write8(SMB2_CHGR_CHRG_EN_CMD, CHRG_ENABLE);
}
void platform_romstage_main(void)
{
/* Watchdog must be checked first to avoid erasing watchdog info later. */
@ -22,6 +45,8 @@ void platform_romstage_main(void)
qclib_rerun();
enable_battery_charging();
/*
* Enable this power rail now for FPMCU stability prior to
* its reset being deasserted in ramstage. This applies