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mb/siemens/mc_rpl1: Adjust USB port settings in devicetree

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In total three USB ports are used:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
Overcurrent reporting is not supported for these ports.

Remove the appropriate UPDs in devicetree and move them to the
variant level to match the hardware configuration.

Change-Id: I9ab02780cfc11f88ddd2bb52bd7fbfb3fdd450ef
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Kilian Krause 2025-06-05 13:13:19 +02:00 • committed by Werner Zeh
commit 6427e51c4f
2 changed files with 30 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

23
src/mainboard/siemens/mc_rpl/devicetree.cb
View file

@ -13,22 +13,6 @@ chip soc/intel/alderlake
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "sata_salp_support" = "1"
register "sata_ports_enable" = "{
@ -181,13 +165,6 @@ chip soc/intel/alderlake
end
end
device ref crashlog off end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device ref xhci_root_hub on end
end
end
device ref sata on end
device ref uart0 on end
device ref gspi0 on end

30
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
View file

@ -3,6 +3,22 @@ chip soc/intel/alderlake
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "true"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is unused
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is unused
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
@ -77,5 +93,19 @@ chip soc/intel/alderlake
end
device ref i2c0 on end
device ref i2c1 on end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device ref xhci_root_hub on
chip drivers/usb/acpi
device ref usb3_port1 on end
end
chip drivers/usb/acpi
device ref usb3_port2 on end
end
end
end
end
end
end