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mb/google/fatcat: Create lapis variant

Browse source 
Create the lapis variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.

BUG=b:438785495
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
        make sure the build includes GOOGLE_LAPIS
     2. Run part_id_gen tool without any errors

Change-Id: Iabcc673a1868cea1d8a650af213d583cc2e27c28
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Hualin Wei 2025-06-23 17:28:15 +08:00 • committed by Matt DeVillier
commit 0eebd5596b
13 changed files with 1017 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

11
src/mainboard/google/fatcat/Kconfig
View file

@ -131,6 +131,13 @@ config BOARD_GOOGLE_KINMEN4ES
config BOARD_GOOGLE_KINMEN
select BOARD_GOOGLE_MODEL_KINMEN
config BOARD_GOOGLE_LAPIS
select BOARD_GOOGLE_BASEBOARD_FATCAT
select FSP_UGOP_EARLY_SIGN_OF_LIFE
select DRIVERS_INTEL_TOUCH
select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD
if BOARD_GOOGLE_FATCAT_COMMON
config BASEBOARD_DIR
@ -168,6 +175,7 @@ config DRIVER_TPM_I2C_BUS
default 0x01 if BOARD_GOOGLE_FRANCKA
default 0x01 if BOARD_GOOGLE_MODEL_FELINO
default 0x03 if BOARD_GOOGLE_MODEL_KINMEN
default 0x03 if BOARD_GOOGLE_LAPIS
config HAVE_SLP_S0_GATE
def_bool n
@ -184,6 +192,7 @@ config MAINBOARD_PART_NUMBER
default "Francka" if BOARD_GOOGLE_FRANCKA
default "Felino" if BOARD_GOOGLE_MODEL_FELINO
default "Kinmen" if BOARD_GOOGLE_MODEL_KINMEN
default "Lapis" if BOARD_GOOGLE_LAPIS
config MEMORY_SOLDERDOWN
def_bool n
@ -196,6 +205,7 @@ config TPM_TIS_ACPI_INTERRUPT
default 79 if BOARD_GOOGLE_MODEL_FELINO # GPE0_DW2_15 (GPP_F15)
default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
default 66 if BOARD_GOOGLE_MODEL_KINMEN # GPE0_DW2_02 (GPP_E02)
default 66 if BOARD_GOOGLE_LAPIS # GPE0_DW2_02 (GPP_E02)
# FIXME: update as per board schematics
config UART_FOR_CONSOLE
@ -211,6 +221,7 @@ config VARIANT_DIR
default "francka" if BOARD_GOOGLE_FRANCKA
default "felino" if BOARD_GOOGLE_MODEL_FELINO
default "kinmen" if BOARD_GOOGLE_MODEL_KINMEN
default "lapis" if BOARD_GOOGLE_LAPIS
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"

3
src/mainboard/google/fatcat/Kconfig.name
View file

@ -37,3 +37,6 @@ config BOARD_GOOGLE_KINMEN4ES
config BOARD_GOOGLE_KINMEN
bool "-> Kinmen"
config BOARD_GOOGLE_LAPIS
bool "-> Lapis"

5
src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
View file

@ -37,6 +37,11 @@
#define GPIO_PCH_WP GPP_D02
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_V17
#elif CONFIG(BOARD_GOOGLE_LAPIS)
#define EC_SYNC_IRQ GPP_E07_IRQ
#define GPIO_PCH_WP GPP_D02
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_V17
#endif
#endif /* __BASEBOARD_GPIO_H__ */

6
src/mainboard/google/fatcat/variants/lapis/Makefile.mk Normal file
View file

@ -0,0 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c

439
src/mainboard/google/fatcat/variants/lapis/gpio.c Normal file
View file

@ -0,0 +1,439 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boardid.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* GPP_A00: ESPI_IO0_EC_R */
/* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
/* GPP_A01: ESPI_IO1_EC_R */
/* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
/* GPP_A02: ESPI_IO2_EC_R */
/* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
/* GPP_A03: ESPI_IO3_EC_R */
/* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
/* GPP_A04: ESPI_CS0_EC_R_N */
/* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
/* GPP_A05: ESPI_CLK_EC_R */
/* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
/* GPP_A06: ESPI_RST_EC_R_N */
/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
/* GPP_A08: Not used */
PAD_NC(GPP_A08, NONE),
/* GPP_A09: Not used */
PAD_NC(GPP_A09, NONE),
/* GPP_A10: Not used */
PAD_NC(GPP_A10, NONE),
/* GPP_A11: Not used */
PAD_NC(GPP_A11, NONE),
/* GPP_A12: WIFI_WAKE_N ==> TOUCHPANEL_SYNC */ /* NC */
PAD_NC(GPP_A12, NONE),
/* GPP_A13: MEM_STRAP_0 */
PAD_CFG_GPI(GPP_A13, NONE, DEEP),
/* GPP_A15: GPP_A15_DNX_FORCE_RELOAD ==> EPD_ON_GCD_OUT*/ /* NC */
/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
/* GPP_A16: BT_DISABLE_L ==> BT_ON_WLAN */
PAD_CFG_GPO(GPP_A16, 1, DEEP),
/* GPP_A17: WIFI_DISABLE_L ==> WLAN_ON_PCH */
PAD_CFG_GPO(GPP_A17, 1, DEEP),
/* GPP_B00: PMC_I2C_PD_SCL ==> PD_SMB1_CLK */
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
/* GPP_B01: PMC_I2C_PD_SDA ==> PD_SMB1_DATA */
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR ==> NC */ /* may be connect to EC */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_NC(GPP_B02, NONE),
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR ==> NC */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_NC(GPP_B03, NONE),
/* GPP_B04: ISH_GP_0_SNSR_HDR ==> NC*/ /* maybe disable ISH */
PAD_NC(GPP_B04, NONE),
/* GPP_B05: ISH_GP_1_SNSR_HDR ==> NC */
PAD_NC(GPP_B05, NONE),
/* GPP_B06: ISH_GP_2_SNSR_HDR ==> NC*/
PAD_NC(GPP_B06, NONE),
/* GPP_B07: ISH_GP_3_SNSR_HDR ==> NC */
PAD_NC(GPP_B07, NONE),
/* GPP_B08: ISH_GP_4_SNSR_HDR ==> GPP_B08_TBT_LOW_POWER_MODE */
PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
/* GPP_B09: M2_GEN5_SSD_RESET_N ==> SSD_GEN5_PERST_L */
PAD_CFG_GPO(GPP_B09, 1, PLTRST),
/* GPP_B10: GEN4_SSD_PWREN */ /* may be NC */
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
/* GPP_B11: MOD_TCSS1_DISP_HPD3 ==> USB_OC1 */ /* may be change to USB_OC1 */
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
/* GPP_B12: PM_SLP_S0_N ==> PCH_SLP_S0# */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* GPP_B13: PLT_RST_N */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B14: MOD_TCSS2_DISP_HPD4 ==> HDMI_HPD_CPU# */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
/* GPP_B15: Not used */
PAD_NC(GPP_B15, NONE),
/* GPP_B16: EN_PP3300_SSD ==> EN_PP3300_SSD_GEN5 */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
/* GPP_B17: Not used ==> GPP_B17_TBT_LOW_POWER_MODE */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF4),
/* GPP_B18: Not used */
PAD_NC(GPP_B18, NONE),
/* GPP_B19: Not used */
PAD_NC(GPP_B19, NONE),
/* GPP_B20: Not used */
PAD_NC(GPP_B20, NONE),
/* GPP_B21: USB4_RT_FORCE_PWR ==> TBT_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B22: Not used */
PAD_NC(GPP_B22, NONE),
/* GPP_B17: Not used */
PAD_NC(GPP_B23, NONE),
/* GPP_B24: MEM_STRAP_3 */
PAD_CFG_GPI(GPP_B24, NONE, DEEP),
/* GPP_B25: DIMM_SEL2 */
PAD_CFG_GPI(GPP_B25, NONE, DEEP),
/* GPP_C00: GPP_C0_SMBCLK ==> SMB_CLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: GPP_C1_SMBDATA ==> SMB_DAT */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C02: Not used */
PAD_NC(GPP_C02, NONE),
/* GPP_C03: TBT_SMB_CLK */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
/* GPP_C04: TBT_SMB_DATA */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
/* GPP_C06: CAM_PWR_EN */ /* TBD */
PAD_CFG_GPO(GPP_C06, 1, DEEP),
/* GPP_C07: MEM_CH_SEL */
PAD_CFG_GPI(GPP_C07, NONE, DEEP),
/* GPP_C08: Not used */
PAD_NC(GPP_C08, NONE),
/* GPP_C09: SSD_GEN5_CLKREQ_ODL ==> CLKREQ0_SSD1# */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
/* GPP_C10: Not used */
PAD_NC(GPP_C10, NONE),
/* GPP_C11: Not used */
PAD_NC(GPP_C11, NONE),
/* GPP_C12: Not used */
PAD_NC(GPP_C12, NONE),
/* GPP_C13: Not used */
PAD_NC(GPP_C13, NONE),
/* GPP_C14: Not used */
PAD_NC(GPP_C14, NONE),
/* GPP_C16: USB_C0_LSX_TX ==> TBT_LSX0_TXD */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17: USB_C0_LSX_RX ==> TBT_LSX0_RXD */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* GPP_C18: Not used */
PAD_NC(GPP_C18, NONE),
/* GPP_C19: Not used */
PAD_NC(GPP_C19, NONE),
/* GPP_C20: USB_C1_LSX_TX ==> TBT_LSX2_TXD */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* GPP_C21: USB_C1_LSX_RX ==> TBT_LSX2_RXD */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* GPP_C22: DDP3_HDMI_CTRLCLK ==> HDMI_X1_CLK*/
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
/* GPP_C23: DDP3_HDMI_CTRLDATA ==> HDMI_X1_DATA */
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
/* GPP_D00: Not used */
PAD_NC(GPP_D00, NONE),
/* GPP_D01: Not used */
PAD_NC(GPP_D01, NONE),
/* GPP_D02: SOC_WP_OD ==> FLASH_WP_CPU */
PAD_CFG_GPI(GPP_D02, NONE, DEEP),
/* GPP_D03: Not used */
PAD_NC(GPP_D03, NONE),
/* GPP_D04: Not used */
PAD_NC(GPP_D04, NONE),
/* GPP_D05: Not used */
PAD_NC(GPP_D05, NONE),
/* GPP_D06: Not used */
PAD_NC(GPP_D06, NONE),
/* GPP_D07: Not used */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: Not used */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: Not used ==> CPU_ID0 */
PAD_NC(GPP_D09, NONE),
/* GPP_D10: Not used ==> CPU_ID1*/
PAD_NC(GPP_D10, NONE),
/* GPP_D11: Not used ==> CPU_ID2*/
PAD_NC(GPP_D11, NONE),
/* GPP_D12: Not used ==> HDA_SDO_PCH */
PAD_NC(GPP_D12, NONE),
/* GPP_D13: Not used ==> HDA_SDI_PCH */
PAD_NC(GPP_D13, NONE),
/* GPP_D14: Not used */
PAD_NC(GPP_D14, NONE),
/* GPP_D15: Not used */
PAD_NC(GPP_D15, NONE),
/* GPP_D16: Not used */ /* DMIC connect to Audio Codec */
PAD_NC(GPP_D16, NONE),
/* GPP_D17: Not used */ /* DMIC connect to Audio Codec */
PAD_NC(GPP_D17, NONE),
/* GPP_D18: Not used */
PAD_NC(GPP_D18, NONE),
/* GPP_D19: Not used */
PAD_NC(GPP_D19, NONE),
/* GPP_D20: EC_SOC_REC_SWITCH_ODL */
PAD_CFG_GPI(GPP_D20, NONE, DEEP),
/* GPP_D21: Not used */
PAD_NC(GPP_D21, NONE),
/* GPP_D22: Not used ==> VPRO_ID0 */
PAD_NC(GPP_D22, NONE),
/* GPP_D23: Not used ==> VPRO_ID1 */
PAD_NC(GPP_D23, NONE),
/* GPP_D24: DIMM_SEL1 */
PAD_CFG_GPI(GPP_D24, NONE, DEEP),
/* GPP_D25: DIMM_SEL0 */
PAD_CFG_GPI(GPP_D25, NONE, DEEP),
/* GPP_E01: Not used */
PAD_NC(GPP_E01, NONE),
/* GPP_E02: GSC_SOC_INT_ODL */ /* locked */
/* PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG), */
/* GPP_E03: Not used */
PAD_NC(GPP_E03, NONE),
/* GPP_E06: Not used */
PAD_NC(GPP_E06, NONE),
/* GPP_E07: EC_SOC_INT_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
/* GPP_E08: Not used */
PAD_NC(GPP_E08, NONE),
/* GPP_E09: USBA0_OC_ODL ==> USB_OC0# */
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
/* GPP_E10: Not used */ /* TPM */
PAD_NC(GPP_E10, NONE),
/* GPP_E11: EN_TCHSCR_PWR ==> TOUCH_ENABLE */
PAD_CFG_GPO(GPP_E11, 1, PLTRST),
/* GPP_E12: SOC_I2C_TCHPAD_SCL ==> THC_I2C0_SCL_TOUCH_EDP */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* GPP_E13: SOC_I2C_TCHPAD_SDA ==> THC_I2C0_SDA_TOUCH_EDP*/
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* GPP_E14: Not used */
PAD_NC(GPP_E14, NONE),
/* GPP_E15: Not used */
PAD_NC(GPP_E15, NONE),
/* GPP_E16: Not used */
PAD_NC(GPP_E16, NONE),
/* GPP_E17: Not used ==> TOUCHPAD_INTR */
PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, NONE),
/* GPP_E18: TCHPAD_INT_ODL_LS ==> Not used */
PAD_NC(GPP_E18, NONE),
/* GPP_E19: Not used ==> PANEL_ID0 */
PAD_NC(GPP_E19, NONE),
/* GPP_E20: Not used ==> PANEL_ID1 */
PAD_NC(GPP_E20, NONE),
/* GPP_E21: PMC_I2C_PD_INT_ODL ==> PD_SMB1_INT# */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* GPP_E22: Not used */
PAD_NC(GPP_E22, NONE),
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
/* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
/* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
/* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
/* GPP_F04: CNV_RF_RESET_R_N */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
/* GPP_F05: CRF_CLKREQ_R */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
/* GPP_F06: Not used */
PAD_NC(GPP_F06, NONE),
/* GPP_F07: Not used */
PAD_NC(GPP_F07, NONE),
/* GPP_F08: Not used */
PAD_NC(GPP_F08, NONE),
/* GPP_F09: NC */
PAD_NC(GPP_F09, NONE),
/* GPP_F10: NC */
PAD_NC(GPP_F10, NONE),
/* GPP_F11: NC */
PAD_NC(GPP_F11, NONE),
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
/* GPP_F14: NC */
PAD_NC(GPP_F14, NONE),
/* GPP_F15: NC */
PAD_NC(GPP_F15, NONE),
/* GPP_F16: THC0_SPI1_RST_N_TCH_PNL1 */
/* THC NOTE: use GPO instead of GPO for THC0 Rst */
PAD_CFG_GPO(GPP_F16, 1, DEEP),
/* GPP_F17: CODEC_INT_N ==> NC */
PAD_NC(GPP_F17, NONE),
/* GPP_F18: SOC_TCHSCR_INT */
PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F19: NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: NC */
PAD_NC(GPP_F20, NONE),
/* GPP_F22: NC */
PAD_NC(GPP_F22, NONE),
/* GPP_H00: Not used */
PAD_NC(GPP_H00, NONE),
/* GPP_H01: Not used */
PAD_NC(GPP_H01, NONE),
/* GPP_H02: Not used */
PAD_NC(GPP_H02, NONE),
/* GPP_H03: Not used */
PAD_NC(GPP_H03, NONE),
/* GPP_H04: Not used */
PAD_NC(GPP_H04, NONE),
/* GPP_H05: Not used */
PAD_NC(GPP_H05, NONE),
/* GPP_H06: SOC_I2C_TPM_SDA */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_H08: UART_DBG_TX_SOC_RX_U */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: UART_SOC_TX_DBG_RX_U */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10: Not used */
PAD_NC(GPP_H10, NONE),
/* GPP_H11: Not used */
PAD_NC(GPP_H11, NONE),
/* GPP_H13: CPU_C10_GATE_L */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: NC */
PAD_NC(GPP_H14, NONE),
/* GPP_H15: NC */
PAD_NC(GPP_H15, NONE),
/* GPP_H16: NC */
PAD_NC(GPP_H16, NONE),
/* GPP_H17: NC */
PAD_NC(GPP_H17, NONE),
/* GPP_H19: NC */
PAD_NC(GPP_H19, NONE),
/* GPP_H20: NC */
PAD_NC(GPP_H20, NONE),
/* GPP_H21: NC */ /* Audio Codec */
PAD_NC(GPP_H21, NONE),
/* GPP_H22: NC */ /* Audio Codec */
PAD_NC(GPP_H22, NONE),
/* GPP_S00: SNDW3_CLK_CODEC */
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
/* GPP_S01: SNDW3_DATA0_CODEC */
PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
/* GPP_S02: SNDW3_DATA1_CODEC */
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
/* GPP_S03: NC */
PAD_NC(GPP_S03, NONE),
/* GPP_S04: SNDW2_CLK */
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
/* GPP_S05: SNDW2_DATA0 */
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
/* GPP_S06: SNDW1_CLK */
PAD_NC(GPP_S06, NONE),
/* GPP_S07: SNDW1_DATA0 */
PAD_NC(GPP_S07, NONE),
/* GPP_V00: BATLOW_L */
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
/* GPP_V01: ACPRESENT */
PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
/* GPP_V02: LANWAKE_N_R */
PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
/* GPP_V03: EC_SOC_PWR_BTN_ODL */
PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
/* GPP_V04: PM_SLP_S3_N */
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
/* GPP_V05: PM_SLP_S4_N */
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
/* GPP_V06: PM_SLP_A_N */
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
/* GPP_V07: SUS_CLK */
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
/* GPP_V08: SLP_WLAN_N */ /* NC */
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
/* GPP_V09: PM_SLP_S5_N */
PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
/* GPP_V10: LANPHYPC_R_N */ /* NC */
PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
/* GPP_V11: PM_SLP_LAN_N */ /* NC */
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
/* GPP_V12: SOC_WAKE_L */
PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
/* GPP_V16: EN_VCCST */
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
/* GPP_V17: SLP_S0_GATE_R */
PAD_CFG_GPO(GPP_V17, 1, DEEP),
/* GPP_VGPIO3_THC0: THC0_WOT */
PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE),
/* GPP_VGPIO3_THC1: THC1_WOT */
PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* GPP_H08: UART0_BUF_RXD */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: UART0_BUF_TXD */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H06: SOC_I2C_TPM_SDA */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_E02: GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
};
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
};
const struct pad_config *variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* Create the stub for romstage gpio, typically use for power sequence */
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
};
DECLARE_CROS_GPIOS(cros_gpios);

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src/mainboard/google/fatcat/variants/lapis/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;

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src/mainboard/google/fatcat/variants/lapis/include/variant/ec.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif /* MAINBOARD_GPIO_H */

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src/mainboard/google/fatcat/variants/lapis/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __MAINBOARD_GPIO_H__
#define __MAINBOARD_GPIO_H__
#include <baseboard/gpio.h>
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __MAINBOARD_GPIO_H__ */

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src/mainboard/google/fatcat/variants/lapis/memory.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <soc/romstage.h>
#include <soc/meminit.h>
static const struct mb_cfg lp5_mem_config = {
.type = MEM_TYPE_LP5X,
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, },
.dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 },
},
.ddr1 = {
.dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, },
.dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 },
},
.ddr2 = {
.dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 },
.dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, },
},
.ddr3 = {
.dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, },
.dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 },
},
.ddr4 = {
.dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 },
.dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, },
},
.ddr5 = {
.dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, },
.dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 },
},
.ddr6 = {
.dq0 = { 9, 10, 11, 8, 14, 12, 13, 15, },
.dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 },
},
.ddr7 = {
.dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, },
.dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 },
},
},
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
},
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {
.ccc_config = 0xFF,
},
};
const struct mb_cfg *variant_memory_params(void)
{
return &lp5_mem_config;
}
int variant_memory_sku(void)
{
/*
* Memory configuration board straps
* MEM_STRAP_0 GPP_A13
* MEM_STRAP_3 GPP_B24
* DIMM_SEL0 GPP_D25
* DIMM_SEL1 GPP_D24
* DIMM_SEL2 GPP_B25
*/
gpio_t spd_gpios[] = {
GPP_A13,
GPP_B24,
GPP_D25,
GPP_D24,
GPP_B25,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
void variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}
bool variant_is_half_populated(void)
{
/* GPIO_MEM_CH_SEL GPP_C07 */
return gpio_get(GPP_C07);
}

7
src/mainboard/google/fatcat/variants/lapis/memory/Makefile.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/lapis/memory src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 0(0b0000) Parts = H58G66CK8BX147, K3KL9L90EM-MGCU, MT62F2G32D4DS-023 WT:C

9
src/mainboard/google/fatcat/variants/lapis/memory/dram_id.generated.txt Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/lapis/memory src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt
DRAM Part Name ID to assign
H58G66CK8BX147 0 (0000)
K3KL9L90EM-MGCU 0 (0000)
MT62F2G32D4DS-023 WT:C 0 (0000)

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src/mainboard/google/fatcat/variants/lapis/memory/mem_parts_used.txt Normal file
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# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.
# Part Name
H58G66CK8BX147
K3KL9L90EM-MGCU
MT62F2G32D4DS-023 WT:C

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src/mainboard/google/fatcat/variants/lapis/overridetree.cb Normal file
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chip soc/intel/pantherlake
register "power_limits_config[PTL_U_1_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_1_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # LED
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 (MB)
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 (DB)
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #1 (MB)/
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 (DB)/
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN"
register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
# Enable EDP in PortA
register "ddi_port_A_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
}"
# Enable CNVi Wi-Fi and Bluetooth
register "cnvi_wifi_core" = "true"
register "cnvi_bt_core" = "true"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C3 | cr50 TPM. |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.logo_valignment = FW_SPLASH_VALIGNMENT_MIDDLE,
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DDR_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""wwan""
## Active Policy
# FIXME: below values are initial reference values only
register "policies.active" = "{
[0] = {
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(70, 97),
TEMP_PCT(65, 90),
TEMP_PCT(60, 80),
TEMP_PCT(55, 75),
TEMP_PCT(50, 65),
TEMP_PCT(45, 45),
TEMP_PCT(43, 30),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(70, 97),
TEMP_PCT(65, 90),
TEMP_PCT(60, 80),
TEMP_PCT(55, 75),
TEMP_PCT(50, 65),
TEMP_PCT(45, 45),
TEMP_PCT(43, 30),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(60, 50),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(60, 60),
TEMP_PCT(55, 50),
TEMP_PCT(50, 40),
TEMP_PCT(45, 30),
}
}
}"
## Passive Policy
# TODO: below values are initial reference values only
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
}"
## Critical Policy
# TODO: below values are initial reference values only
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}"
## Power Limits Control
register "controls.power_limits" = "{
.pl1 = {
.min_power = 25000,
.max_power = 25000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 95000,
.max_power = 95000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
## Fan Performance Control (Percent, Speed, Noise, Power)
register "controls.fan_perf" = "{
[0] = { 90, 6700, 220, 2200, },
[1] = { 80, 5800, 180, 1800, },
[2] = { 70, 5000, 145, 1450, },
[3] = { 60, 4900, 115, 1150, },
[4] = { 50, 3838, 90, 900, },
[5] = { 40, 2904, 55, 550, },
[6] = { 30, 2337, 30, 300, },
[7] = { 20, 1608, 15, 150, },
[8] = { 10, 800, 10, 100, },
[9] = { 0, 0, 0, 50, }
}"
## Fan options
register "options.fan.fine_grained_control" = "true"
register "options.fan.step_size" = "2"
device generic 0 alias dptf_policy on end
end
end
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "4"
# DDIA for eDP
register "device[0].name" = ""LCD0""
register "device[0].type" = "panel"
# DDIB for HDMI
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
device generic 0 on end
end
end
device ref ipu on end
device ref iaa off end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp2 on end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref tcss_usb3_port0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device ref tcss_usb3_port2 on end
end
end
end
end
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port0 as dfp[0].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port2 as dfp[0].typec_port
device generic 0 on end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 LED""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(3, 1)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 0""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(4, 1)"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port 1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(5, 1)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi
register "desc" = ""User Facing Camera""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "true"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)"
register "enable_delay_ms" = "20"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Fingerprint""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(7, 1)"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 0""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(4, 2)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port 1""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(5, 2)"
device ref usb3_port2 on end
end
end
end
end
device ref pcie_rp9 on
register "pcie_rp[PCIE_RP(9)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "is_storage" = "true"
register "srcclk_pin" = "0"
device generic 0 on end
end
end # Gen4 SSD
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "add_acpi_dma_property" = "true"
register "enable_cnvi_ddr_rfim" = "true"
use cnvi_bluetooth as bluetooth_companion
device generic 0 on end
end
end # CNVi
device ref cnvi_bluetooth on end
device ref thc0 on
register "thc_wake_on_touch[0]" = "true"
# THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled.
chip drivers/intel/touch
register "name" = "INTEL_THC0_NAME"
register "mode" = "THC_HID_I2C_MODE"
register "dev_hidi2c.hid" = ""RAYD0001""
register "dev_hidi2c.cid" = ""PNP0C50""
register "dev_hidi2c.intf.hidi2c.addr" = "0x39"
register "dev_hidi2c.intf.hidi2c.descriptor_address" = "0x1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E11)"
register "wake_on_touch" = "true"
# NOTE: Use GpioInt() in _CRS and does not use GPE.
register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)"
register "active_ltr" = "1"
register "idle_ltr" = "0"
register "connected_device" = "TH_SENSOR_GENERIC"
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end #Touchpenal
device ref thc1 on
register "thc_wake_on_touch[1]" = "true"
chip drivers/intel/touch
register "name" = "INTEL_THC1_NAME"
register "mode" = "THC_HID_I2C_MODE"
register "wake_on_touch" = "true"
# NOTE: Use GpioInt() in _CRS and does not use GPE.
register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)"
register "active_ltr" = "1"
register "idle_ltr" = "0"
register "connected_device" = "TH_SENSOR_GENERIC"
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end #Touchpad
device ref i2c0 on end
device ref i2c3 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E02_IRQ)"
device i2c 50 on end
end
end # I2C3
end
end