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mb/siemens/mc_rpl1: Adjust I2C bus enablement in devicetree

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This mainboard only uses I2C0 and I2C1. Disable all the others. Move I2C
configuration from baseboard to variant.

Change-Id: I0c554ea4da948bc96d6a392c39bcb07a25a79eb4
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88880
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kilian Krause 2025-06-23 10:30:35 +02:00 • committed by Werner Zeh
commit 296f5968d3
2 changed files with 21 additions and 112 deletions
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112
src/mainboard/siemens/mc_rpl/devicetree.cb
View file

@ -58,15 +58,6 @@ chip soc/intel/alderlake
register "s0ix_enable" = "true"
register "dptf_enable" = "true"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
@ -108,21 +99,6 @@ chip soc/intel/alderlake
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
@ -257,96 +233,8 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref i2c0 on end
device ref i2c1 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM0""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "ssdb.vcm_type" = "0x0C"
register "vcm_name" = ""VCM0""
register "num_freq_entries" = "1"
register "link_freq[0]" = "450000000"
register "remote_name" = ""IPU0""
register "has_power_resource" = "true"
#Controls
register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on end
end
chip drivers/intel/mipi_camera
register "acpi_uid" = "3"
register "acpi_name" = ""VCM0""
register "chip_name" = ""DW AF VCM""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
register "vcm_compat" = ""dongwoon,dw9714""
device i2c 0C on end
end
end
device ref i2c2 on end
device ref i2c3 on end
device ref heci1 on end
device ref sata on end
device ref i2c5 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM1""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "num_freq_entries" = "1"
register "link_freq[0]" = "450000000"
register "remote_name" = ""IPU0""
register "has_power_resource" = "true"
#Controls
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on end
end
end
device ref uart0 on end
device ref gspi0 on end
device ref p2sb on end

21
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
View file

@ -3,6 +3,25 @@ chip soc/intel/alderlake
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "true"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
}"
# Intel Common SoC Config
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
@ -56,5 +75,7 @@ chip soc/intel/alderlake
.flags = PCIE_RP_CLK_REQ_UNUSED,
}"
end
device ref i2c0 on end
device ref i2c1 on end
end
end