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mb/siemens/mc_rpl: Remove unused devices from devicetree and Kconfig

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Remove unused device entries from devicetree.cb and Kconfig files for
PCIe, audio, camera, WiFi and Bluetooth.

Change-Id: I8c45736e0f7f6887a0863c72c4ca2e6854b4349d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88881
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kilian Krause 2025-06-23 18:16:36 +02:00 • committed by Werner Zeh
commit 71c4619045
2 changed files with 1 additions and 86 deletions
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25
src/mainboard/siemens/mc_rpl/Kconfig
View file

@ -5,25 +5,16 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
select BOARD_ROMSIZE_KB_16384
select CPU_INTEL_SOCKET_LGA1700
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_I2C_MAX98373
select DRIVERS_INTEL_DPTF
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_INTEL_SOUNDWIRE
select DRIVERS_SOUNDWIRE_ALC_BASE_7XX
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select USE_SIEMENS_HWILIB
config BOARD_SIEMENS_MC_RPL1
select BOARD_SIEMENS_BASEBOARD_MC_RPL
select DRIVERS_UART_8250IO
select GEN3_EXTERNAL_CLOCK_BUFFER
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_RAPTORLAKE
@ -68,20 +59,4 @@ config DRIVER_TPM_SPI_BUS
config USE_PM_ACPI_TIMER
default n if BOARD_SIEMENS_MC_RPL1
config GEN3_EXTERNAL_CLOCK_BUFFER
bool
depends on SOC_INTEL_ALDERLAKE_PCH_P
default n
help
Support external Gen-3 clock chip for ADL-P.
`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` provides feed clock to discrete buffer
for further distribution to platform. SRCCLKREQB[7:9] maps to internal
SRCCLKREQB[6]. If any of them asserted, SRC buffer
`CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER` gets enabled.
config CLKSRC_FOR_EXTERNAL_BUFFER
depends on GEN3_EXTERNAL_CLOCK_BUFFER
int
default 6 # CLKSRC 6
endif

62
src/mainboard/siemens/mc_rpl/devicetree.cb
View file

@ -10,9 +10,6 @@ chip soc/intel/alderlake
# FSP configuration
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
@ -48,13 +45,6 @@ chip soc/intel/alderlake
[3] = 1,
}"
# Enable EDP in PortA
register "ddi_portA_config" = "1"
# Enable HDMI in Port B
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
register "s0ix_enable" = "true"
register "dptf_enable" = "true"
@ -85,14 +75,6 @@ chip soc/intel/alderlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# HD Audio
register "pch_hda_dsp_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
register "cnvi_bt_audio_offload" = "true"
# Intel Common SoC Config
register "common_soc_config" = "{
.gspi[1] = {
@ -198,42 +180,14 @@ chip soc/intel/alderlake
device generic 0 alias dptf_policy on end
end
end
device ref ipu on
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{2,2}"
register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
register "cio2_prt[0]" = "2"
register "cio2_prt[1]" = "1"
device generic 0 on end
end
end
device ref crashlog off end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
end
device ref xhci_root_hub on end
end
end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref heci1 on end
device ref sata on end
device ref uart0 on end
device ref gspi0 on end
@ -246,20 +200,6 @@ chip soc/intel/alderlake
device spi 0 on end
end
end
device ref hda on
chip drivers/intel/soundwire
device generic 0 on
chip drivers/soundwire/alc711
# SoundWire Link 0 ID 1
register "desc" = ""Headset Codec""
register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
register "alc711_address.class" = "MIPI_CLASS_NONE"
register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
device generic 0.1 on end
end
end
end
end
device ref smbus on end
end
end