soc/power9/rom_media.c: find CBFS in PNOR
Tested on QEMU with ECC. Use mmap_helper to handle loading of compressed ramstage. Bootblock fits in SEEPROM with both console and LZ4 romstage compression, but not with verbose CBFS debug messages. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I91c72c52849eb1e3fafe43390351537d04382e46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Krystian Hebel
Matt DeVillier
parent
44ec090551
commit
8f2633cd60
2 changed files with 441 additions and 1 deletions
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@ -8,7 +8,9 @@
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/* Set MSB to 1 to ignore HRMOR */
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#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
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#define LPCHC_IO_SPACE 0xD0010000
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#define LPCHC_FW_SPACE 0xF0000000
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#define FLASH_IO_SPACE 0xFC000000
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#define FW_SPACE_SIZE 0x10000000
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#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
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#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE)
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#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000
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@ -1,8 +1,446 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <string.h>
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#include <boot_device.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <endian.h>
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#include <cbfs.h>
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#include <symbols.h>
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#include "../../../../3rdparty/ffs/ffs/ffs.h"
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#define LPC_FLASH_MIN (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_FW_SPACE)
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#define LPC_FLASH_TOP (LPC_FLASH_MIN + FW_SPACE_SIZE)
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#define CBFS_PARTITION_NAME "HBI"
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/* ffs_entry is not complete in included ffs.h, it lacks user data layout.
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* See https://github.com/open-power/skiboot/blob/master/libflash/ffs.h */
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/* Data integrity flags */
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#define FFS_ENRY_INTEG_ECC 0x8000
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/* Version Checking : 1 byte */
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#define FFS_VERS_SHA512 0x80
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enum ecc_status {
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CLEAN = 0, //< No ECC Error was detected.
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CORRECTED = 1, //< ECC error detected and corrected.
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UNCORRECTABLE = 2 //< ECC error detected and uncorrectable.
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};
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typedef enum ecc_status ecc_status_t;
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enum ecc_bitfields {
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GD = 0xff, //< Good, ECC matches.
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UE = 0xfe, //< Uncorrectable.
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E0 = 71, //< Error in ECC bit 0
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E1 = 70, //< Error in ECC bit 1
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E2 = 69, //< Error in ECC bit 2
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E3 = 68, //< Error in ECC bit 3
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E4 = 67, //< Error in ECC bit 4
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E5 = 66, //< Error in ECC bit 5
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E6 = 65, //< Error in ECC bit 6
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E7 = 64 //< Error in ECC bit 7
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};
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/*
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static uint64_t ecc_matrix[] = {
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//0000000000000000111010000100001000111100000011111001100111111111
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0x0000e8423c0f99ff,
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//0000000011101000010000100011110000001111100110011111111100000000
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0x00e8423c0f99ff00,
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//1110100001000010001111000000111110011001111111110000000000000000
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0xe8423c0f99ff0000,
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//0100001000111100000011111001100111111111000000000000000011101000
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0x423c0f99ff0000e8,
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//0011110000001111100110011111111100000000000000001110100001000010
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0x3c0f99ff0000e842,
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//0000111110011001111111110000000000000000111010000100001000111100
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0x0f99ff0000e8423c,
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//1001100111111111000000000000000011101000010000100011110000001111
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0x99ff0000e8423c0f,
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//1111111100000000000000001110100001000010001111000000111110011001
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0xff0000e8423c0f99
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};
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*/
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/*
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* Compressed version of table above, saves 48 bytes. Rotating value in register
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* results in exactly the same size as full table, due to cost of loading values
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* into registers.
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*/
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static uint8_t ecc_matrix[] = {
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0x00, 0x00, 0xe8, 0x42, 0x3c, 0x0f, 0x99, 0xff,
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0x00, 0x00, 0xe8, 0x42, 0x3c, 0x0f, 0x99
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};
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static uint8_t syndrome_matrix[] = {
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GD, E7, E6, UE, E5, UE, UE, 47, E4, UE, UE, 37, UE, 35, 39, UE,
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E3, UE, UE, 48, UE, 30, 29, UE, UE, 57, 27, UE, 31, UE, UE, UE,
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E2, UE, UE, 17, UE, 18, 40, UE, UE, 58, 22, UE, 21, UE, UE, UE,
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UE, 16, 49, UE, 19, UE, UE, UE, 23, UE, UE, UE, UE, 20, UE, UE,
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E1, UE, UE, 51, UE, 46, 9, UE, UE, 34, 10, UE, 32, UE, UE, 36,
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UE, 62, 50, UE, 14, UE, UE, UE, 13, UE, UE, UE, UE, UE, UE, UE,
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UE, 61, 8, UE, 41, UE, UE, UE, 11, UE, UE, UE, UE, UE, UE, UE,
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15, UE, UE, UE, UE, UE, UE, UE, UE, UE, 12, UE, UE, UE, UE, UE,
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E0, UE, UE, 55, UE, 45, 43, UE, UE, 56, 38, UE, 1, UE, UE, UE,
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UE, 25, 26, UE, 2, UE, UE, UE, 24, UE, UE, UE, UE, UE, 28, UE,
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UE, 59, 54, UE, 42, UE, UE, 44, 6, UE, UE, UE, UE, UE, UE, UE,
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5, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
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UE, 63, 53, UE, 0, UE, UE, UE, 33, UE, UE, UE, UE, UE, UE, UE,
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3, UE, UE, 52, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
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7, UE, UE, UE, UE, UE, UE, UE, UE, 60, UE, UE, UE, UE, UE, UE,
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UE, UE, UE, UE, 4, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE, UE,
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};
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static inline uint32_t rd32(void *addr)
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{
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uint64_t ret;
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/* Cache-inhibited load word */
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asm volatile("lwzcix %0, 0, %1"
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: "=r" (ret)
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: "r" (addr)
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: );
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return ret;
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}
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static uint64_t rd64_unaligned(void *addr, int first_read)
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{
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static uint64_t tmp1; /* static is used to reduce number of PNOR reads */
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uint64_t tmp2;
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uint64_t ret;
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uint64_t addr_aligned = ALIGN_DOWN((uint64_t)addr, 8);
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unsigned int shift = 8 * ((uint64_t) addr - addr_aligned);
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if (shift == 0 /* Previous tmp2 ended with ECC byte */
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|| first_read) { /* or it is the first invocation from remove_ecc */
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asm volatile("ldcix %0, 0, %1"
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: "=r" (tmp1)
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: "r" (addr_aligned)
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: );
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}
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asm volatile("ldcix %0, 0, %1"
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: "=r" (tmp2)
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: "r" (addr_aligned+8)
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: );
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ret = (tmp1 << shift) | (tmp2 >> (64 - shift));
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tmp1 = tmp2;
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return ret;
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}
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/*
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* memcpy from cache-inhibited source
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*
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* Assume src is 8B-aligned and does not overlap with dest. Copies ALIGN(n,8)
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* bytes, make sure dest is big enough.
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*/
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static inline void memcpy_ci_src(void *dest, const void *src, size_t n)
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{
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int i;
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uint64_t tmp;
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for (i = 0; i < n; i += 8) {
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asm volatile("ldcix %0, %1, %2"
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: "=r" (tmp)
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: "b"(src), "r" (i));
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asm volatile("stdx %0, %1, %2"
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:: "r" (tmp), "b"(dest), "r" (i)
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: "memory");
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}
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}
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static uint8_t generate_ecc(uint64_t i_data)
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{
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uint8_t result = 0;
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for (int i = 0; i < 8; i++)
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result |= __builtin_parityll((*(uint64_t *)&ecc_matrix[i]) & i_data) << i;
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return result;
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}
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static uint8_t verify_ecc(uint64_t i_data, uint8_t i_ecc)
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{
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return syndrome_matrix[generate_ecc(i_data) ^ i_ecc];
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}
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static uint8_t correct_ecc(uint64_t *io_data, uint8_t *io_ecc)
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{
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uint8_t bad_bit = verify_ecc(*io_data, *io_ecc);
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if ((bad_bit != GD) && (bad_bit != UE)) { /* Good is done, UE is hopeless */
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/* Determine if the ECC or data part is bad, do bit flip. */
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if (bad_bit >= E7)
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*io_ecc ^= (1 << (bad_bit - E7));
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else
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*io_data ^= (1ull << (63 - bad_bit));
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}
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return bad_bit;
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}
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static ecc_status_t remove_ecc(uint8_t *io_src, size_t i_srcSz,
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uint8_t *o_dst, size_t i_dstSz)
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{
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ecc_status_t rc = CLEAN;
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int first_read = 1;
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for (size_t i = 0, o = 0; i < i_srcSz;
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i += sizeof(uint64_t) + sizeof(uint8_t), o += sizeof(uint64_t)) {
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/*
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* Read data and ECC parts. Reads from cache-inhibited storage always
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* have to be aligned!
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*/
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uint64_t data = rd64_unaligned(&io_src[i], first_read);
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first_read = 0;
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uint8_t ecc = io_src[i + sizeof(uint64_t)];
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/* Calculate failing bit and fix data */
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uint8_t bad_bit = correct_ecc(&data, &ecc);
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/* Perform correction and status update */
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if (bad_bit == UE)
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rc = UNCORRECTABLE;
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/* Unused, our source is not writable */
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/*
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else if (bad_bit != GD)
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{
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if (rc != UNCORRECTABLE)
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{
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rc = CORRECTED;
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}
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*(uint64_t*)(&io_src[i]) = data;
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io_src[i + sizeof(uint64_t)] = ecc;
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}
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*/
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/* Copy fixed data to destination buffer */
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*(uint64_t *)(&o_dst[o]) = data;
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}
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return rc;
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}
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static char *pnor_base;
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/*
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* PNOR has to be accessed with Cache Inhibited forms of instructions, and they
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* require that the address is aligned, so we can just memcpy the data.
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*/
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static ssize_t no_ecc_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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uint8_t tmp[8];
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offset -= rd->region.offset;
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size_t off_a = ALIGN_DOWN(offset, 8);
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size_t size_left = size;
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char *part_base = pnor_base + rd->region.offset;
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/* If offset is not 8B-aligned */
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if (offset & 0x7) {
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int i;
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memcpy_ci_src(tmp, &part_base[off_a], 8);
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for (i = 8 - (offset & 7); i < 8; i++) {
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*((uint8_t *)(b++)) = tmp[i];
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if (!--size_left)
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return size;
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}
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off_a += 8;
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}
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/* Align down size_left to 8B */
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memcpy_ci_src(b, &part_base[off_a], ALIGN_DOWN(size_left, 8));
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/* Copy the rest of requested unaligned data, if any */
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if (size_left & 7) {
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off_a += ALIGN_DOWN(size_left, 8);
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b += ALIGN_DOWN(size_left, 8);
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int i;
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memcpy_ci_src(tmp, &part_base[off_a], 8);
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for (i = 0; i < (size_left & 7); i++)
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*((uint8_t *)(b++)) = tmp[i];
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}
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return size;
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}
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static ssize_t ecc_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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uint8_t tmp[8];
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offset -= rd->region.offset;
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size_t off_a = ALIGN_DOWN(offset, 8);
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size_t size_left = size;
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char *part_base = pnor_base + rd->region.offset;
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/* If offset is not 8B-aligned */
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if (offset & 0x7) {
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int i;
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remove_ecc((uint8_t *) &part_base[(off_a * 9)/8], 9, tmp, 8);
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for (i = 8 - (offset & 7); i < 8; i++) {
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*((uint8_t *)(b++)) = tmp[i];
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if (!--size_left)
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return size;
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}
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off_a += 8;
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}
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/* Align down size_left to 8B */
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remove_ecc((uint8_t *) &part_base[(off_a * 9)/8],
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(ALIGN_DOWN(size_left, 8) * 9) / 8,
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b,
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ALIGN_DOWN(size_left, 8));
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/* Copy the rest of requested unaligned data, if any */
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if (size_left & 7) {
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off_a += ALIGN_DOWN(size_left, 8);
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b += ALIGN_DOWN(size_left, 8);
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int i;
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remove_ecc((uint8_t *) &part_base[(off_a * 9)/8], 9, tmp, 8);
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for (i = 0; i < (size_left & 7); i++)
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*((uint8_t *)(b++)) = tmp[i];
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}
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return size;
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}
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static struct region_device_ops no_ecc_rdev_ops = {
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.mmap = mmap_helper_rdev_mmap,
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.munmap = mmap_helper_rdev_munmap,
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.readat = no_ecc_readat,
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};
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static struct region_device_ops ecc_rdev_ops = {
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.mmap = mmap_helper_rdev_mmap,
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.munmap = mmap_helper_rdev_munmap,
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.readat = ecc_readat,
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};
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static void mount_part_from_pnor(const char *part_name,
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struct mmap_helper_region_device *mdev)
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{
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size_t base, size;
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unsigned int i, block_size, entry_count = 0;
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struct ffs_hdr *hdr_pnor = (struct ffs_hdr *)LPC_FLASH_TOP;
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/* This loop could be skipped if we may assume that PNOR is always 64M */
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while (hdr_pnor > (struct ffs_hdr *)LPC_FLASH_MIN) {
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uint32_t csum = 0;
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/* Size is aligned up to 8 because of how memcpy_ci_src works */
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uint8_t buffer[ALIGN(FFS_HDR_SIZE, 8)];
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struct ffs_hdr *hdr = (struct ffs_hdr *)buffer;
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/* Assume block_size = 4K */
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hdr_pnor = (struct ffs_hdr *)(((char *)hdr_pnor) - 0x1000);
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if (rd32(&hdr_pnor->magic) != FFS_MAGIC)
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continue;
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if (rd32(&hdr_pnor->version) != FFS_VERSION_1)
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continue;
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/* Copy the header so we won't have to rd32() for further accesses */
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memcpy_ci_src(buffer, hdr_pnor, FFS_HDR_SIZE);
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csum = hdr->magic ^ hdr->version ^ hdr->size ^ hdr->entry_size ^
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hdr->entry_count ^ hdr->block_size ^ hdr->block_count ^
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hdr->resvd[0] ^ hdr->resvd[1] ^ hdr->resvd[2] ^ hdr->resvd[3] ^
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hdr->checksum;
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if (csum != 0)
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continue;
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pnor_base = (char *) LPC_FLASH_TOP - hdr->block_size * hdr->block_count;
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entry_count = hdr->entry_count;
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block_size = hdr->block_size;
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/* Every byte counts when building for SEEPROM */
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if (!CONFIG(BOOTBLOCK_IN_SEEPROM)) {
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printk(BIOS_DEBUG, "FFS header at %p\n", hdr_pnor);
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printk(BIOS_SPEW, " size %x\n", hdr->size);
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printk(BIOS_SPEW, " entry_size %x\n", hdr->entry_size);
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printk(BIOS_SPEW, " entry_count %x\n", hdr->entry_count);
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printk(BIOS_SPEW, " block_size %x\n", hdr->block_size);
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printk(BIOS_SPEW, " block_count %x\n", hdr->block_count);
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printk(BIOS_DEBUG, "PNOR base at %p\n", pnor_base);
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}
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break;
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}
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if (hdr_pnor <= (struct ffs_hdr *)LPC_FLASH_MIN)
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die("FFS header not found!\n");
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for (i = 0; i < entry_count; i++) {
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uint32_t *val, csum = 0;
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int j;
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/* Size is aligned up to 8 because of how memcpy_ci_src works */
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uint8_t buffer[ALIGN(FFS_ENTRY_SIZE, 8)];
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struct ffs_entry *e = (struct ffs_entry *)buffer;
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/* Copy the entry so we won't have to rd32() for further accesses */
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memcpy_ci_src(buffer, &hdr_pnor->entries[i], FFS_ENTRY_SIZE);
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/* Every byte counts when building for SEEPROM */
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if (!CONFIG(BOOTBLOCK_IN_SEEPROM)) {
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printk(BIOS_SPEW, "%s: base %x, size %x (%x)\n\t type %x, flags %x\n",
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e->name, e->base, e->size, e->actual, e->type, e->flags);
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}
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if (strcmp(e->name, part_name) != 0)
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continue;
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val = (uint32_t *) e;
|
||||
for (j = 0; j < (FFS_ENTRY_SIZE / sizeof(uint32_t)); j++)
|
||||
csum ^= val[j];
|
||||
|
||||
if (csum != 0)
|
||||
continue;
|
||||
|
||||
base = block_size * e->base;
|
||||
/* This is size of the partition, it does not include header or ECC */
|
||||
size = e->actual;
|
||||
|
||||
mdev->rdev.ops = &no_ecc_rdev_ops;
|
||||
|
||||
if (e->user.data[0] & FFS_ENRY_INTEG_ECC) {
|
||||
printk(BIOS_DEBUG, "%s partition has ECC\n", part_name);
|
||||
mdev->rdev.ops = &ecc_rdev_ops;
|
||||
size = size / 9 * 8;
|
||||
}
|
||||
|
||||
if ((e->user.data[1] >> 24) & FFS_VERS_SHA512) {
|
||||
/* Skip PNOR partition header */
|
||||
base += 0x1000;
|
||||
|
||||
/* Possibly skip ECC of the header */
|
||||
if (e->user.data[0] & FFS_ENRY_INTEG_ECC)
|
||||
base += 0x200;
|
||||
}
|
||||
|
||||
mdev->rdev.region.offset = base;
|
||||
mdev->rdev.region.size = size;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct mmap_helper_region_device boot_mdev = MMAP_HELPER_DEV_INIT(
|
||||
&no_ecc_rdev_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache);
|
||||
|
||||
void boot_device_init(void)
|
||||
{
|
||||
static int init_done;
|
||||
if (init_done)
|
||||
return;
|
||||
|
||||
mount_part_from_pnor(CBFS_PARTITION_NAME, &boot_mdev);
|
||||
|
||||
init_done = 1;
|
||||
}
|
||||
|
||||
const struct region_device *boot_device_ro(void)
|
||||
{
|
||||
return NULL;
|
||||
return &boot_mdev.rdev;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue