mb/erying/tgl: Clean up the GPIO table
Looks nicer, fixes DisplayPort and edge-cases where PCIe devices weren't detected at random. Change-Id: Ie00f2258e95eb6a44e1f71f462c8ca33c4184870 Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88714 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Alicja Michalska
Felix Singer
parent
179b8444c3
commit
762a535551
1 changed files with 203 additions and 225 deletions
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@ -3,93 +3,89 @@
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1), // ESPI_IO0
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // ESPI_IO1
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // ESPI_IO2
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // ESPI_IO3
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // ESPI_CS0#
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PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1), // ESPI_CLK
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PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1), // ESPI_RESET#
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PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1), // ESPI_CS1#
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PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1), // ESPI_CS2#
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PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1), // ESPI_CS3#
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PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALERT0#
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PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // ESPI_ALERT1#
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PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // ESPI_ALERT2#
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PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // ESPI_ALERT3#
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_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
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/* ------- GPIO Group GPP_R ------- */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
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PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
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PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
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PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
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PAD_NC(GPP_R5, NONE),
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_PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
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_PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
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_PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
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PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1), // PCIE_LNK_DOWN
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PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1), // ISH_UART0_RTS#
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PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1), // SX_EXIT_HOLDOFF#
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_PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKOUT_48 */
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_PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ISH_GP7 */
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PAD_NC(GPP_R14, NONE),
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PAD_NC(GPP_R15, NONE),
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PAD_NC(GPP_R16, NONE),
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PAD_NC(GPP_R17, NONE),
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PAD_CFG_GPO(GPP_R18, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_R19, NONE),
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PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1), // ESPI_IO0
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // ESPI_IO1
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // ESPI_IO2
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // ESPI_IO3
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // ESPI_CS0#
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PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1), // ESPI_CLK
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PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1), // ESPI_RESET#
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PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1), // ESPI_CS1#
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PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1), // ESPI_CS2#
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PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1), // ESPI_CS3#
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PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALERT0#
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PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // ESPI_ALERT1#
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PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // ESPI_ALERT2#
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PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // ESPI_ALERT3#
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PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), // Unknown
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/* ------- GPIO Group GPP_B ------- */
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PAD_CFG_GPO(GPP_B0, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_B0, 1, PLTRST), // GPO, some kind of VR?
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PAD_NC(GPP_B1, NONE),
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PAD_NC(GPP_B2, NONE),
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PAD_NC(GPP_B3, NONE),
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PAD_NC(GPP_B4, NONE),
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PAD_NC(GPP_B5, NONE),
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PAD_NC(GPP_B6, NONE),
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PAD_NC(GPP_B7, NONE),
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // SRCCLKREQ3
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PAD_NC(GPP_B9, NONE),
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PAD_NC(GPP_B10, NONE),
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PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPIO */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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PAD_NC(GPP_B13, NONE),
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PAD_NC(GPP_B14, NONE),
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// We don't know the mapping of SRCCLKREQs because vendor refused to share schematics. Leave their configuration to the FSP.
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PAD_CFG_GPO(GPP_B11, 1, DEEP), // GPO, some kind of VR?
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPK_BEEP
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_CLK */
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_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_MISO */
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_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GSPI1_MOSI */
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PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_B20, NONE),
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1), // SMBCLK
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PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1), // SMBDATA
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PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1), // SMBALERT#
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL
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PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // SML0ALERT#
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF2), // I2C3_SDA
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF2), // I2C3_SCL
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PAD_NC(GPP_C8, NONE),
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_CFG_GPO(GPP_C12, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C14, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C0_SDA
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C0_SCL
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // I2C1_SDA
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // I2C1_SCL
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PAD_NC(GPP_C20, NONE),
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PAD_NC(GPP_C21, NONE),
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE),
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_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1CLK */
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_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RF_RESET# */
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_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* MODEM_CLKREQ */
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PAD_CFG_NF(GPP_D4, NONE, RSMRST, NF1), // SML1CLK
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PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNV_RF_RESET#
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF2), // MODEM_CLKREQ
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */
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_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */
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PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_D12, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0CLK
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0DATA
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PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_D12, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1DATA */
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PAD_CFG_NF(GPP_D15, NONE, RSMRST, NF1), // SML1DATA
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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@ -99,41 +95,46 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_C ------- */
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_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBCLK */
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_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBDATA */
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PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
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_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SDA */
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_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SCL */
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PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */
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_PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SDA */
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_PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SCL */
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PAD_NC(GPP_C8, NONE),
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_CFG_GPO(GPP_C12, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C14, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPIO */
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_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SDA */
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_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SCL */
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_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SDA */
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_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SCL */
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PAD_NC(GPP_C20, NONE),
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PAD_NC(GPP_C21, NONE),
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), // SATAXPCIE0
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PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), // SATAXPCIE1
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PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), // SATA_DEVSLP0
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PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // SATA_DEVSLP1
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PAD_CFG_GPO(GPP_E6, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_E7, NONE),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATALED#
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PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), // USB_OC0#
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PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), // USB_OC1#
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PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), // USB_OC2#
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PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), // USB_OC3#
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/* ------- GPIO Group GPP_S ------- */
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_PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_CLK */
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_PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_DATA */
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_PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_CLK */
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_PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_DATA */
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_PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA1 */
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_PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA1 */
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_PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA0 */
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_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA0 */
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, NONE, PLTRST, NF1), // SATAXPCIE3
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PAD_CFG_NF(GPP_F1, NONE, PLTRST, NF1), // SATAXPCIE4
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PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), // SATAXPCIE5
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PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F4, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F5, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_F6, NONE),
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PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_F8, NONE),
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PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_F10, NONE),
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PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F12, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_F13, 1, PLTRST), /* GPIO */
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PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), // PS_ON#
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PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPP_F16, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_F17, NONE),
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PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */
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PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_NC(GPP_F21, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPO(GPP_F23, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_NC(GPP_G0, NONE),
|
||||
|
|
@ -141,148 +142,125 @@ static const struct pad_config gpio_table[] = {
|
|||
PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_G3, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_DRAM# */
|
||||
PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), // SLP_DRAM#
|
||||
PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_G7, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLCLK */
|
||||
_PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLDATA */
|
||||
_PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLCLK */
|
||||
_PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLDATA */
|
||||
_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLCLK */
|
||||
_PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLDATA */
|
||||
_PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLCLK */
|
||||
_PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLDATA */
|
||||
|
||||
/* ------- GPIO Community 2 ------- */
|
||||
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */
|
||||
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */
|
||||
PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */
|
||||
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */
|
||||
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
|
||||
PAD_NC(GPD12, NONE), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 3 ------- */
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */
|
||||
PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */
|
||||
PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* SATA_DEVSLP0 */
|
||||
PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA_DEVSLP1 */
|
||||
PAD_CFG_GPO(GPP_E6, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* SATALED# */
|
||||
PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), /* USB_OC0# */
|
||||
PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), /* USB_OC1# */
|
||||
PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), /* USB_OC2# */
|
||||
PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), /* USB_OC3# */
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE3 */
|
||||
_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE4 */
|
||||
_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE5 */
|
||||
PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F4, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F5, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F12, 1, DEEP), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F13, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), /* PS_ON# */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_F16, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_VDDEN */
|
||||
_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTEN */
|
||||
_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTCTL */
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_CFG_GPO(GPP_F23, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
PAD_NC(GPP_G8, NONE),
|
||||
PAD_NC(GPP_G9, NONE),
|
||||
PAD_NC(GPP_G10, NONE),
|
||||
PAD_NC(GPP_G11, NONE),
|
||||
PAD_CFG_NF(GPP_G12, NATIVE, DEEP, NF1), // DDP1_CTRLCLK
|
||||
PAD_CFG_NF(GPP_G13, NATIVE, DEEP, NF1), // DDP1_CTRLDATA
|
||||
PAD_CFG_NF(GPP_G14, NATIVE, DEEP, NF1), // DDP2_CTRLCLK
|
||||
PAD_CFG_NF(GPP_G15, NATIVE, DEEP, NF1), // DDP2_CTRLDATA
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_NC(GPP_H0, NONE),
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
PAD_NC(GPP_H2, NONE),
|
||||
PAD_NC(GPP_H3, NONE),
|
||||
PAD_NC(GPP_H4, NONE),
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // SRCCLKREQ12
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // SRCCLKREQ13
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SRCCLKREQ14
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SRCCLKREQ15
|
||||
PAD_CFG_GPO(GPP_H10, 1, PLTRST), // GPIO */
|
||||
|
||||
// We don't know the mapping of SRCCLKREQs because vendor refused to share schematics. Leave their configuration to the FSP.
|
||||
|
||||
PAD_CFG_GPO(GPP_H10, 1, PLTRST), // GPIO */
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H16, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_GPO(GPP_J0, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CPU_C10_GATE# */
|
||||
_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_BRI_DT */
|
||||
_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */
|
||||
_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RGI_DT */
|
||||
_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */
|
||||
PAD_NC(GPP_J6, NONE),
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_J8, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_J9, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K1, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K2, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDA */
|
||||
_PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDB */
|
||||
_PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID0 */
|
||||
_PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID1 */
|
||||
PAD_CFG_GPO(GPP_K10, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PMCALERT# */
|
||||
_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD1 */
|
||||
_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDSP_HPD2 */
|
||||
_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD3 */
|
||||
_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD4 */
|
||||
_PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */
|
||||
_PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* DDPB_CTRLDATA */
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_CFG_GPO(GPP_I8, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_I9, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_I10, 1, PLTRST), /* GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SDA */
|
||||
_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SCL */
|
||||
_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB_OC6# */
|
||||
_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C5_SCL */
|
||||
PAD_CFG_NF(GPP_I0, NONE, RSMRST, NF1), // PMCALERT#
|
||||
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DDSP_HPD1
|
||||
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // DDSP_HPD2
|
||||
PAD_NC(GPP_I3, NONE),
|
||||
PAD_NC(GPP_I4, NONE),
|
||||
PAD_CFG_NF(GPP_I5, NATIVE, DEEP, NF1), // DDPB_CTRLCLK
|
||||
PAD_CFG_NF(GPP_I6, NATIVE, DEEP, NF1), // DDPB_CTRLDATA
|
||||
PAD_CFG_NF(GPP_I7, NATIVE, DEEP, NF1), // DDPC_CTRLCLK
|
||||
PAD_CFG_NF(GPP_I8, NATIVE, DEEP, NF1), // DDPC_CTRLDATA
|
||||
PAD_CFG_GPO(GPP_I9, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_I10, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2), // I2C4_SDA
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2), // I2C4_SCL
|
||||
PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), // USB_OC6#
|
||||
PAD_CFG_NF(GPP_I14, NONE, DEEP, NF2), // I2C5_SCL
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_GPO(GPP_J0, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPO(GPP_J8, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_J9, 1, PLTRST), /* GPIO */
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K1, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K2, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
|
||||
PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
|
||||
PAD_NC(GPP_K6, NONE),
|
||||
PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), // DDSP_HPDB
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // CORE_VID0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // CORE_VID1
|
||||
PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1), // DDSP_HPDC
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDO
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDI
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
// Using HDA instead of SOF, disable I2S
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_R8, NONE),
|
||||
PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1), // PCIE_LNK_DOWN
|
||||
PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1), // ISH_UART0_RTS#
|
||||
PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1), // SX_EXIT_HOLDOFF#
|
||||
PAD_CFG_NF(GPP_R12, NATIVE, DEEP, NF1), // CLKOUT_48
|
||||
PAD_CFG_NF(GPP_R13, NATIVE, DEEP, NF1), // ISH_GP7
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
PAD_NC(GPP_R16, NONE),
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_CFG_GPO(GPP_R18, 1, PLTRST), // GPO, some kind of VR?
|
||||
PAD_NC(GPP_R19, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S (SoundWire - unused) ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // ACPRESENT
|
||||
PAD_CFG_NF(GPD2, NATIVE, PLTRST, NF1), // LAN_WAKE#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PLTRST, NF1), // PWRBTN#
|
||||
PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), // SLP_S3#
|
||||
PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), // SLP_S4#
|
||||
PAD_CFG_NF(GPD6, NONE, PLTRST, NF1), // SLP_A#
|
||||
PAD_CFG_GPO(GPD7, 1, PLTRST), // GPIO
|
||||
PAD_CFG_NF(GPD8, NONE, PLTRST, NF1), // SUSCLK
|
||||
PAD_CFG_NF(GPD9, NONE, PLTRST, NF1), // SLP_WLAN#
|
||||
PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), // SLP_S5#
|
||||
PAD_CFG_NF(GPD11, NONE, PLTRST, NF1), // LANPHYPC
|
||||
PAD_NC(GPD12, NONE), // GPIO
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue