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mb/erying/tgl: Map remaining USB ports

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All USB ports are working \o/

Change-Id: I49aa8a245f656b8b6e47ce3a0e69899c052cf3f3
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88716
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Alicja Michalska 2025-08-08 02:30:50 +02:00 • committed by Felix Singer
commit 23e92a5ac0
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/erying/tgl/devicetree.cb
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@ -74,10 +74,13 @@ chip soc/intel/tigerlake
[3] = USB2_PORT_MID(OC_SKIP), /* NIC right */
[4] = USB2_PORT_MID(OC_SKIP), /* Front Panel 1 */
[5] = USB2_PORT_MID(OC_SKIP), /* Front Panel 2 */
[6] = USB2_PORT_MID(OC_SKIP), /* Front Panel 3 */
[7] = USB2_PORT_MID(OC_SKIP), /* Front Panel 4 */
[8] = USB2_PORT_MID(OC_SKIP), /* Front Panel 1 (USB3) */
[9] = USB2_PORT_MID(OC_SKIP), /* Front Panel 2 (USB3) */
[10] = USB2_PORT_MID(OC_SKIP), /* Rear, top left */
[11] = USB2_PORT_MID(OC_SKIP), /* Rear, top right */
[12] = USB2_PORT_MID(OC_SKIP), /* M.2 NGFF (Bluetooth) */
}"
register "usb3_ports" = "{