This mainboard uses native function two of GPIO B23 (PCHHOT_N) to
realise overtemperature behaviour of the mainboard.
TEST=Check the signal during HW commissioning and influence of heat to
the CPU.
Change-Id: I4caa88316d5027f7b9d74293a74377915f274766
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90085
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable PCIe PTM (Precision Time Measurement) for all enabled PCIe root
ports. The time synchronization is mainly necessary for stable timing to
PLC.
TEST
Boot in a standard linux OS and check if PTM ist enabled for active RPs
via lspci -vv -s 00:1c.0..6 | grep PTM
Change-Id: I965ab349c07158d0c69b9112571aa98575eada77
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90084
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Adapt I2C controller configuration for mc_ehl6 board. This involves
changes to the coreboot I2C setup. To prevent higher I2C speeds from
being used by the OS, dummy devices are installed on the I2C bus.
TEST=Check if drivers for the I2C devices started correctly during
coreboot execution and verify that all I2C devices are detected in the
OS.
Change-Id: I6de578f969456a15807a1380209ea18e01f522bd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds the Display Stream Compression (DSC) related structures
to the panel header. These structures define the rate control parameters
and configuration options required by the DSC engine for frame
compression, such as quantization parameter ranges, bits per group
offset, compression enable flag, dual DSC support, and line buffer
depth.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Icec24f55b962cd2794a79a68fc8fecec43300103
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90129
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is one too many `endif` in this file. The only reason why jenkins
never complained is because this is apparently never included (and
therefore never compiled) by any code/mainboard in our tree.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id68d91d5c5365000fc97815d184d48f4b71bcb35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Adds skeleton code so that the HEST ACPI table is included as part of
the ACPI tables propagated to the OS.
The ACPI table can be included by mainboards by selecting
SOC_AMD_COMMON_BLOCK_ACPI_HEST.
TEST=Select the option, build the mainboard and see the output in Linux:
[ 0.282277] HEST: Table parsing has been initialized.
Change-Id: I69886a19764d6974cbe129a8a6bf717f7808fb08
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88113
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
This moves all the definitions and declarations that are part of the
ACPI Platform Error Interface (APEI) into the corresponding header file.
Change-Id: Ied3915e4f598cd393f396de26b07ade7ce3a7ab1
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Increase the bootblock size to 70K to accommodate its growth, e.g.,
CB:90147 and CB:89157.
This commit also conditionally includes the DRAM_INIT_CODE section when
ENV_ROMSTAGE is enabled, and the BOOTBLOCK section otherwise. This
allows increased BOOTBLOCK overlapping with DRAM_INIT_CODE as these two
sections won't be utilized in the same boot stage.
TEST=emerge-geralt coreboot
Change-Id: Ib7b930fbb1815d2f24b9618d94a38d02c66eab97
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90251
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Modify usb3 port 0 and 1 settings by vendor's advices.
BUG=b:446771934
TEST=Build and boot to OS, check usb3 functions work by lsusb -t.
Change-Id: I9ed47ead1b2ef0b007897513ceb99e9460875bdc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This change mutes the amplifier by updating the HDA verb table boot beep
section, which is configured at boot time. The amplifier will be unmuted when
generating a dev beep to preserve that functionality.
After entering OS, the kernel will reset the drivers and re-enable the
speaker.
BUG=b:457933720
TEST=Play audio in the OS and reboot the device. Verify that no pop
noise is heard from the speakers.
TEST=Verify devbeep function
Change-Id: I19ef19533d8ed7522e638787c8179ae0fdbf1ebb
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90238
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The renoir variant has larger APOB data.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b7da3b35f2795deb785f82326f3e6c640f6e9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Renoir actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45d6b559874d67b886c65f7ad722f96eba415399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90211
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unable to passthrough the UART0 in domU when UART1 enabled in dom0
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7ccf366dbac556f68096382644f3e72b13e2dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90210
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig.
It only writes the MSRs of the APs if they are not initialized yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45771e596ac4354dd233a47fcae33012d9c0a6c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The TYPE17_DMI_INFO struct in renoir FSP has the SMBIOS 3.2 layout, not
the SMBIOS 3.3 layout. The struct definition in the coreboot code needs
to match the one that the FSP uses when creating the DMI into HOB.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icd45d4e25dcc4a5977deaeba2b178e0b9dd1e453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
If you reworked the board its possible NVME reset is attached to GPIO 40
instead of 24.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib2a10701ed2c3e677419f700a69277c2cde588f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Due to "firmware.PDProtocol" item of FAFT PD test result has failed
and the HDMI function can't work on USB type C of the daughter board
side when the DUT with 1C+5G of daughter board config.
Add missing settings for WWAN to pass the test.
BUG=b:463200834
TEST=emerge-nissa coreboot chromeos-bootimage
Check 5G LTE module detectable by command # mmcli -m a.
Confirm firmware.PDProtocol PASS.
Change-Id: I8657e383ed376c4a3af328f7593d5503babe2e3d
Signed-off-by: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90170
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase I2C0 touchpad tHD to 0.53 us by adjusting data_hold_time_ns in
I2C0 from 50 to 250, the new tHD meets SPEC between 0.3 us and 0.9 us.
The setting format is copied from baseboard/brox and modify I2C0.
BUG=b:461977573
TEST=emerge-brox coreboot
checked TP function work
measure the wave form meets SPEC
Before: tHD ~0.072 us
After: tHD ~0.53 us
Change-Id: I2841107a9165fc0eacc465fe5013d23856a3f755
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This commit adds the relevant DIDs to support Tiger Lake H (TGL-H) systems based on the Xeon W-11865MRE (GPU) and RM590E chipset (PCH).
TEST=A platform with Xeon W-11865MRE and RM590E booted
the relevant information printed in coreboot log.
[DEBUG] CPU: ID 806d1, Tigerlake R0, ucode: 00000056
[DEBUG] MCH: device id 9a36 (rev 05) is Tigerlake-H-8-1
[DEBUG] PCH: device id 4390 (rev 11) is Tigerlake-H RM590E
[DEBUG] IGD: device id 9a70 (rev 01) is Tigerlake H GT1 32EU
Change-Id: I2bff2551b9f194e169c0edd080e9c869bcc9c60f
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90179
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
K3KL8L80EM-MGCV
Because there are some attributes of MT62F1G32D2DS-020 WT:D and
K3KL8L80EM-MGCV when review the specification again,
so modify the memory_parts.json attributes and re-generate SPD id
for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV.
BUG=b:446771934
TEST=Use part_id_gen to generate related settings
Change-Id: Ic38286f38c4c6572cf2e22c78f5f202cc0a152cc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
A pop noise is heard from the speakers on caboc devices when rebooting
while audio is playing.
This is caused by the speaker amplifier (class-D) being active during
the reboot process.
This change mutes the amplifier by updating the HDA verb table, which
is configured at boot time. The amplifier will be unmuted when
generating a dev beep to preserve that functionality.
BUG=b:439638686
TEST=Play audio in the OS and reboot the device. Verify that no pop
noise is heard from the speakers.
Change-Id: Ic9980d31097d60ede879c8d6dcdd541580765795
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement full support for the LB_BOOT_MODE_OFFMODE_CHARGING
state. This mode is detected when the system powers on due to an
external charging event (cable insertion) while the system was
previously fully powered off.
This boot mode is critical for systems that need to maintain a light
footprint to quickly start charging without performing a full boot.
It combines with the existing low-battery mode to define a unified
"low power boot" state.
In romstage, the boot mode is detected using is_off_mode() and
the EC's low battery status, and the result is saved to CBMEM. In
ramstage, this mode is read to determine if heavy, resource-intensive
initializations should be skipped to conserve time and power.
Key changes:
- In romstage.c, implement set_boot_mode() to determine the
mode (NORMAL, OFFMODE_CHARGING, or LOW_BATTERY) and save it to
CBMEM_ID_BOOT_MODE.
- In mainboard.c, introduce get_boot_mode() and
is_low_power_boot() to retrieve and check the CBMEM value.
- Skip heavy ramstage initializations (mainboard_init and
mainboard_needs_pcie_init) when in a low-power boot mode.
- Update lb_add_boot_mode to report the mode stored in CBMEM
to the coreboot table.
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I57d25deb6b2b1f9ff199cea5ca2953f10ffb4746
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90176
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new CBMEM ID, CBMEM_ID_BOOT_MODE (0x444D5442, "BTMD"),
to provide a dedicated storage location for the system's detected
boot mode (e.g., normal boot, low-battery, off-mode boot etc).
Storing the boot mode in CBMEM ensures that the initial detection
performed early in the boot process (e.g., in romstage by reading
PMIC logs) is securely passed to subsequent stages like ramstage,
where different boot modes require distinct logic paths.
Key changes:
- Define CBMEM_ID_BOOT_MODE in cbmem_id.h.
- Add "BOOT MODE" entry to the CBMEM_ID_TO_NAME_TABLE.
BUG=b:439819922
TEST=Verify boot mode stored in CBMEM.
Change-Id: I7ebf29385a99ac1be491bfefe1c74c8c9e58b55d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90175
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the is_off_mode() detection API on the Bluey mainboard
to call the newly introduced SOC-specific PMIC function,
is_pon_on_ac().
This change delegates the complex Power-On (PON) log parsing and
PMIC register checking to the SOC layer, simplifying the mainboard
code base. The board layer now contains only the high-level policy
wrapper for detecting cable-power-on events.
This improves modularity and ensures the board code relies on the
correct hardware abstraction.
Key changes:
- Implement is_off_mode() as a simple wrapper around is_pon_on_ac()
(from the SOC PMIC library).
- Include soc/pmic.h to access the SOC's PMIC APIs.
- Expose is_off_mode() in board.h.
BUG=b:439819922
TEST=Verify boot mode on Google/Quenbi.
Change-Id: Ibc13c3ad96846cf5b3fb9bcf461e3f338ac9b8bd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add the Power-On (PON) history log parsing and status API to the
SOC layer (soc/qualcomm/x1p42100/pmic.c).
This code is specific to the Qualcomm PMIC architecture (reading
registers for PON events and reasons), making it an SOC-specific
utility rather than a board-level policy. Moving it here improves
modularization and allows other X1p42100-based boards to reuse this
critical power management logic.
Key APIs introduced:
- pm_pon_read_pon_hist(): Reads the raw circular PON event log
from the PMIC, reverses the buffer to put the latest entry first.
- is_pon_on_ac(): Interprets the log to detect if the power-on
reason was due to AC/Cable Power (PON_CBLPWR_RSN).
Key changes:
- Create src/soc/qualcomm/x1p42100/include/soc/pmic.h with PON
definitions and API prototypes.
- Create src/soc/qualcomm/x1p42100/pmic.c containing the PON
log reading and parsing logic.
- Add pmic.c to the SOC's romstage build via Makefile.mk.
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I8cd1478b9f8d53519f603e8f5168d0a51fa54971
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90192
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API, spmi_read_bytes(), to allow reading a
sequence of registers from a Qualcomm PMIC using the SPMI bus.
While the existing spmi_read8() is suitable for single-byte
access, reading large log areas (like the PON history log)
requires iterating over a contiguous block of addresses. This
new function encapsulates the required loop, calling spmi_read8()
sequentially for each address in the range.
This abstraction improves code cleanliness and makes high-level PMIC
log parsing much simpler.
Key changes:
- Define spmi_read_bytes() prototype in qcom_spmi.h.
- Implement spmi_read_bytes() in spmi.c to perform sequential
reads using spmi_read8().
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I6017336a882a8fa8d771b0127e78dd4f0fdbdd0e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the SPMI_ADDR macro to wrap both the slave and reg
arguments in parentheses.
The previous definition, ((slave << 16) | reg), led to incorrect
address calculation when the slave argument was an arithmetic or
logical expression (e.g., (a | b)), as the bit-shift operator (<<)
has higher precedence than the logical OR (|).
The revised macro guarantees that the full slave expression is
evaluated before the bit shift, ensuring correct SPMI register
address construction.
Key changes:
- Wrap slave and reg arguments in parentheses within
SPMI_ADDR definition.
BUG=b:439819922
TEST=Verify that the SPMI_ADDR output is correct.
e.g. SPMI_ADDR(0x02 | 0x01, 0x200)
Output before this change:
```
((0x02 | 0x01 << 16) | 0x200)
(0x02 | 0x010000 | 0x200)
(0x010202)
```
Output after this change:
```
(((0x02 | 0x01) << 16) | 0x200)
(((0x03) << 16) | 0x200)
((0x030000) | 0x200)
(0x030200)
```
Change-Id: I58b36b62f0b5a59c03a1c1d08640fe9086d81d7a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the GT domain Thermal Design Current (TDC) value for the
PTL_TDC_1 SKU from 15A to 23A to align with the latest hardware
specifications. The previous value was inconsistent with the intended
power map, which could lead to incorrect power delivery settings and
potential system instability. This change ensures compliance with
Document #813289, revision 2.1.
Change-Id: Ib6b4ddc422de62585658b5e8464d598762b947ee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Align the IA domain Thermal Design Current (TDC) value for PTL_TDC_2
with Document #813289 power map revision 2.1. The previous value 23A did
not match the updated specification, which now requires 28A. This change
ensures that the firmware correctly reflects the hardware power limits
for this SKU, preventing potential power delivery issues and improving
system stability.
Change-Id: I16bb510b8ec2ad1ffdeba20bfe26d0cbad209088
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SKU_7 ICC Max and TDC were not accurate. This commit aligns SKU_7
settings with document #813278 - Panther Lake H Platform Power Map
2.1.1.
Change-Id: Ia66ca5c0d2dc1ba0f0cf3b21476e83923e49969e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit refactors the Panther Lake SoC power mapping and
configuration to support distinct Thermal Design Current (TDC) settings
for each TDP variant and SKU. Previously, TDC values were mapped
directly to SKUs, which limited flexibility and could lead to incorrect
current settings for CPUs with the same SKU but different TDP
requirements.
TEST=On a Fatcat device with a 25W TDP, the FSP logs show that the
appropriate TDC settings were applied.
Change-Id: Ie645110e9ff200ecb601faf427958ded731fb22b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89932
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Because the proto and evt build use the same panel but different
controllers, so add proto touch panel address to fit two controllers.
BUG=b:452216678
TEST=Build FW and boot to OS, check touch function works.
Change-Id: Ia9a3764ffe85aa69ba1c4c3f4ae8fd2717e1e570
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Its useful if you have some binaries downstream which are not published
yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I00f67e6eb93af095e3ae1f4851d13cd7666a9851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the option to enable M.2 SDD slot to Kconfig file instead of using
a macro. Its already used like a Kconfig option later on, so the if
condition actually works now.
Change-Id: I104eae5501da6ed1fe43039f88d6722c1e54e82d
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove the gpio function calls from ec code and mode to early gpio file.
Change-Id: I941828808bdcdac00ab59d48907da1f70024d6e0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87442
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicate code and make it into a single function to
read the board revision from ec.
Change-Id: If7f3e7eda2c43417639494880a080fa472474cab
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If XGBE is used on the platform, it can be configured to match different
use cases.
Change-Id: Ia6f7c2b836050e52bfb1d9ff64745d83715c874b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90104
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FSP folder for Renoir and include it in the build from soc/cezanne
path. Cezanne and Renoir are very similar but there are still enough
changes to justify a separate vendorcode directory.
Change-Id: Id7f51a70c02ea632d87a635e92a6c422ac369bef
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 04778ddd38 ("drivers/option/cfr: Remove old sm_object from
constructor") updated the function signature for CFR callbacks, but the
commits adding the fan and backlight controls were merged afterwards
without being adjusted accordingly. Do so here.
TEST=build/boot google/link with these CFR options enabled.
Change-Id: I9ea5224a820b014c4c8edb93e8a6b336ea6f58d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Six years ago we had a problem with not getting SError exceptions in
coreboot, and we fixed it by setting the right SCR_EL3 bits to force
exception routing to EL3 (commit bb345abbfc ("arm64: Correctly unmask
asynchronous SError interrupts")). Turns out that we have the same
problem in the payload but we never fixed it there. EL2 exception
routing works differently, so in order to achieve the same effect here
we can either enable the HCR_EL2 AMO, FMO and IMO bits (respectively),
or we can just enable the TGE bit which traps everything. This patch
chooses the latter, and it also ensures that the PSTATE exception
masking (DAIF) bits are in the expected state (although they usually
already are).
This state will persist after handoff to the kernel or chained payload,
and will prevent transition into EL1 if not cleared first. This should
be fine since any code taking control in EL2 should be expected to
correctly reintialize HCR_EL2 before handing off into EL1 (the Linux
kernel has always reinitialized this very early after its entry point).
If any selfboot() payloads are broken after this change, the payload
should be fixed to reinitialize HCR_EL2 to 0 (or desired value).
Change-Id: I339eded5a5344b5753c94be82e4f1e52e00b39f4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.
BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4bcbb34e1d53b3438f9e9f2b39f09d91e8dc7110
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89982
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure and enable the PCIe root ports and associated clocks for the
mc_ehl6 mainboard. This is necessary because the PCIe configuration
differs from the mc_ehl2 baseboard.
TEST=Boot into the OS and verify that all expected PCIe devices are
correctly detected.
Change-Id: Ie5ac3d437088d1db08f869317ef3e5712c3baa3e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl2 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.
Further specific adaptations for the mc_ehl6 hardware will be handled
in subsequent commits.
Change-Id: Ifcc730da492edb084e67762ce643f27b1a2576b0
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.
Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.
BUG=b:433636690
TEST=emerge-skywalker coreboot
TEST="elogtool list" contained "Hardware watchdog reset"
BRANCH=skywalker
Change-Id: Iac6ec72d5c148244ccbd7d1b02af78c359897d7d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90174
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the watchdog timeout triggers a reset, the CPU will return to the
default frequency. If there is a mismatch between voltage and frequency,
the device will fail to reboot. Therefore, the kernel configuration
"mediatek,disable-extrst" is removed for MT8189, meaning the watchdog
timeout will trigger external reset, by notifying PMIC and EC via
AP_PMIC_WDTRST_L.
As we want to keep the watchdog status registers until coreboot runs,
the MT8189's EC simply ignores the external reset signal
AP_PMIC_WDTRST_L. Because EC ignores it, coreboot has to trigger the
secondary reset by another method other than watchdog hardware.
Therefore, introduce a Kconfig option MEDIATEK_WDT_RESET_BY_SW to
trigger the secondary reset by board_reset(), which is often implemented
by asserting a GPIO (for example GPIO_AP_EC_WARM_RST_REQ for MT8189).
BUG=b:433636690
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: Ib4c698bfd1b85705be05f40f385f4e252975c319
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90172
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8189, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
Fortunately, the Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is also
enabled. Therefore, even if WATCHDOG_TOMBSTONE data is cleared, the
elog_handle_watchdog_tombstone() function can still obtain the correct
watchdog reset reason from EC.
On MT8189, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8189 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:433636690, b:456672760
TEST=emerge-skywalker coreboot
TEST=watchdog event added to eventlog on WDT timeout
TEST=cbmem logs preserved on WDT timeout
BRANCH=skywalker
Change-Id: Id1cfc2700301ebb0b6399356b884b2473c883445
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Update EN_SPK_PA pin configuration based on the schematic to enable speaker function.
schematics: RUBY_EVT_0902_2112.pdf
BUG=b:452216678
TEST=Build FW and boot to OS, verify that the speaker is functioning
by playing a YouTube video.
Change-Id: Iabb3e9d214841aaa155ce5b782740ad0722722fa
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90169
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
