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vc/amd/fsp/cezanne: Add Renoir FSP

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Add FSP folder for Renoir and include it in the build from soc/cezanne
path. Cezanne and Renoir are very similar but there are still enough
changes to justify a separate vendorcode directory.

Change-Id: Id7f51a70c02ea632d87a635e92a6c422ac369bef
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Ana Carolina Cabral 2025-04-17 10:27:17 -03:00 • committed by Felix Held
commit f61553c9fa
15 changed files with 730 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

11
src/soc/amd/cezanne/Makefile.mk
View file

@ -17,6 +17,8 @@ bootblock-y += early_fch.c
bootblock-y += espi_util.c
romstage-y += fsp_m_params.c
romstage-$(CONFIG_SOC_AMD_CEZANNE) += fsp_m_params_cezanne.c
romstage-$(CONFIG_SOC_AMD_RENOIR) += fsp_m_params_renoir.c
ramstage-y += acpi.c
ramstage-y += chip.c
@ -36,9 +38,16 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
endif
ifeq ($(CONFIG_SOC_AMD_RENOIR),y)
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/renoir
endif
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40

5
src/soc/amd/cezanne/chip.h
View file

@ -11,7 +11,12 @@
#include <soc/southbridge.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <types.h>
#if CONFIG(SOC_AMD_CEZANNE)
#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
#elif CONFIG(SOC_AMD_RENOIR)
#include <vendorcode/amd/fsp/renoir/FspUsb.h>
#endif
struct soc_amd_cezanne_config {
struct soc_amd_common_config common_config;

13
src/soc/amd/cezanne/fsp_m_params.c
View file

@ -13,8 +13,9 @@
#include <static.h>
#include <string.h>
#include <types.h>
#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
#include "chip.h"
#include "fsp_m_params.h"
__weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
{
@ -169,15 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->usb_phy_ptr = 0;
}
if (config->edp_phy_override) {
mcfg->edp_phy_override = config->edp_phy_override;
mcfg->edp_physel = config->edp_physel;
mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
}
platform_fsp_memory_init_params_cb_sub(mcfg, config);
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);

7
src/soc/amd/cezanne/fsp_m_params.h Normal file
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@ -0,0 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/api.h>
#include "chip.h"
void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
const struct soc_amd_cezanne_config *config);

18
src/soc/amd/cezanne/fsp_m_params_cezanne.c Normal file
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@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include "fsp_m_params.h"
void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
const struct soc_amd_cezanne_config *config)
{
if (config->edp_phy_override) {
mcfg->edp_phy_override = config->edp_phy_override;
mcfg->edp_physel = config->edp_physel;
mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
}
}

9
src/soc/amd/cezanne/fsp_m_params_renoir.c Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "chip.h"
#include "fsp_m_params.h"
void platform_fsp_memory_init_params_cb_sub(FSP_M_CONFIG *mcfg,
const struct soc_amd_cezanne_config *config)
{
}

24
src/vendorcode/amd/fsp/renoir/FspGuids.h Normal file
View file

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __FSP_GUIDS__
#define __FSP_GUIDS__
#include <uuid.h>
#define AMD_FSP_TSEG_HOB_GUID \
GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
#define AMD_FSP_ACPI_ALIB_HOB_GUID \
GUID_INIT(0x42494c41, 0x4002, 0x403b, \
0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)
#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \
GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \
0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C )
#define AMD_FSP_CCX_CPPC_DATA_HOB_GUID \
GUID_INIT(0x3060C5EC, 0x7399, 0x432D, \
0xBC, 0x97, 0xBF, 0x95, 0xE4, 0x3D, 0x53, 0x0C )
#endif /* __FSP_GUIDS__ */

20
src/vendorcode/amd/fsp/renoir/FspUpd.h Normal file
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@ -0,0 +1,20 @@
/** @file
*
* This file is automatically generated.
*
*/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#ifdef EFI32
# include <FspEas.h>
# include <stdint.h>
#else
# include <fsp_h_c99.h>
#endif
#define FSPM_UPD_SIGNATURE 0x4D5F31305F444D41 /* 'RENOIR_M' */
#define FSPS_UPD_SIGNATURE 0x535F31305F444D41 /* 'RENOIR_S' */
#endif

59
src/vendorcode/amd/fsp/renoir/FspUsb.h Normal file
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@ -0,0 +1,59 @@
#ifndef __FSPUSB_H__
#define __FSPUSB_H__
#include <FspUpd.h>
#define FSP_USB_STRUCT_MAJOR_VERSION 0xd
#define FSP_USB_STRUCT_MINOR_VERSION 0x6
#define USB2_PORT_COUNT 8
#define USB3_PORT_COUNT 4
#define USBC_COMBO_PHY_COUNT 2
struct fch_usb2_phy {
uint8_t compdstune; ///< COMPDSTUNE
uint8_t sqrxtune; ///< SQRXTUNE
uint8_t txfslstune; ///< TXFSLSTUNE
uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE
uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE
uint8_t txrisetune; ///< TXRISETUNE
uint8_t txvreftune; ///< TXVREFTUNE
uint8_t txhsxvtune; ///< TXHSXVTUNE
uint8_t txrestune; ///< TXRESTUNE
} __packed;
struct fch_usb3_phy {
uint8_t tx_term_ctrl; ///< tx_term_ctrl
uint8_t rx_term_ctrl; ///< rx_term_ctrl
uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN
uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL
} __packed;
#define USB0_PORT0 0
#define USB0_PORT1 1
#define USB0_PORT2 1
#define USB0_PORT3 3
#define USB1_PORT0 (0<<2)
#define USB1_PORT1 (1<<2)
#define USB1_PORT2 (1<<2)
#define USB1_PORT3 (3<<2)
#define USB_COMBO_PHY_MODE_USB_C 0
#define USB_COMBO_PHY_MODE_USB_ONLY 1
#define USB_COMBO_PHY_MODE_USB_DPM 2
#define USB_COMBO_PHY_MODE_USB_DPP 3
struct usb_phy_config {
uint8_t Version_Major; ///< USB IP version
uint8_t Version_Minor; ///< USB IP version
uint8_t TableLength; ///< TableLength
uint8_t Reserved0;
struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength
struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment
uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
uint8_t Reserved2[4];
} __packed;
#endif

124
src/vendorcode/amd/fsp/renoir/FspmUpd.h Normal file
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@ -0,0 +1,124 @@
/** @file
*
* This file is _NOT_ automatically generated in coreboot!
*
*/
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
#include <FspUpd.h>
#include <FspUsb.h>
#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT 14
#define FSPM_UPD_DDI_DESCRIPTOR_COUNT 5
/** Fsp M Configuration
**/
typedef struct __packed {
/** Offset 0x0040**/ uint32_t bert_size;
/** Offset 0x0044**/ uint32_t tseg_size;
/** Offset 0x0048**/ uint32_t pci_express_base_addr;
/** Offset 0x004C**/ uint8_t misc_reserved[32];
/** Offset 0x006C**/ uint32_t serial_port_base;
/** Offset 0x0070**/ uint32_t serial_port_use_mmio;
/** Offset 0x0074**/ uint32_t serial_port_baudrate;
/** Offset 0x0078**/ uint32_t serial_port_refclk;
/** Offset 0x007C**/ uint32_t serial_reserved;
/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
/** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets;
/** Offset 0x0359**/ uint8_t pcie_reserved[51];
/** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
/** Offset 0x03A0**/ uint8_t ddi_reserved[6];
/** Offset 0x03A6**/ uint8_t ccx_down_core_mode;
/** Offset 0x03A7**/ uint8_t ccx_disable_smt;
/** Offset 0x03A8**/ uint8_t ccx_reserved[32];
/** Offset 0x03C8**/ uint8_t stt_control;
/** Offset 0x03C9**/ uint8_t stt_pcb_sensor_count;
/** Offset 0x03CA**/ uint16_t stt_min_limit;
/** Offset 0x03CC**/ uint16_t stt_m1;
/** Offset 0x03CE**/ uint16_t stt_m2;
/** Offset 0x03D0**/ uint16_t stt_m3;
/** Offset 0x03D2**/ uint16_t stt_m4;
/** Offset 0x03D4**/ uint16_t stt_m5;
/** Offset 0x03D6**/ uint16_t stt_m6;
/** Offset 0x03D8**/ uint16_t stt_c_apu;
/** Offset 0x03DA**/ uint16_t stt_c_gpu;
/** Offset 0x03DC**/ uint16_t stt_c_hs2;
/** Offset 0x03DE**/ uint16_t stt_alpha_apu;
/** Offset 0x03E0**/ uint16_t stt_alpha_gpu;
/** Offset 0x03E2**/ uint16_t stt_alpha_hs2;
/** Offset 0x03E4**/ uint16_t stt_skin_temp_apu;
/** Offset 0x03E6**/ uint16_t stt_skin_temp_gpu;
/** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2;
/** Offset 0x03EA**/ uint16_t stt_error_coeff;
/** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient;
/** Offset 0x03EE**/ uint8_t smartshift_enable;
/** Offset 0x03EF**/ uint32_t apu_only_sppt_limit;
/** Offset 0x03F3**/ uint32_t sustained_power_limit;
/** Offset 0x03F7**/ uint32_t fast_ppt_limit;
/** Offset 0x03FB**/ uint32_t slow_ppt_limit;
/** Offset 0x03FF**/ uint8_t system_configuration;
/** Offset 0x0400**/ uint8_t cppc_ctrl;
/** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range;
/** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range;
/** Offset 0x0403**/ uint8_t cppc_epp_max_range;
/** Offset 0x0404**/ uint8_t cppc_epp_min_range;
/** Offset 0x0405**/ uint8_t cppc_preferred_cores;
/** Offset 0x0406**/ uint8_t stapm_boost;
/** Offset 0x0407**/ uint32_t stapm_time_constant;
/** Offset 0x040B**/ uint32_t slow_ppt_time_constant;
/** Offset 0x040F**/ uint32_t thermctl_limit;
/** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9];
/** Offset 0x041C**/ uint8_t iommu_support;
/** Offset 0x041D**/ uint8_t pspp_policy;
/** Offset 0x041E**/ uint8_t enable_nb_azalia;
/** Offset 0x041F**/ uint8_t audio_io_ctl;
/** Offset 0x0420**/ uint8_t pdm_mic_selection;
/** Offset 0x0421**/ uint8_t hda_enable;
/** Offset 0x0422**/ uint8_t nbio_reserved[31];
/** Offset 0x0441**/ uint32_t emmc0_mode;
/** Offset 0x0445**/ uint16_t emmc0_init_khz_preset;
/** Offset 0x0447**/ uint8_t emmc0_sdr104_hs400_driver_strength;
/** Offset 0x0448**/ uint8_t emmc0_ddr50_driver_strength;
/** Offset 0x0449**/ uint8_t emmc0_sdr50_driver_strength;
/** Offset 0x044A**/ uint8_t UnusedUpdSpace0[85];
/** Offset 0x049F**/ uint32_t gnb_ioapic_base;
/** Offset 0x04A3**/ uint8_t gnb_ioapic_id;
/** Offset 0x04A4**/ uint8_t fch_ioapic_id;
/** Offset 0x04A5**/ uint8_t sata_enable;
/** Offset 0x04A6**/ uint8_t fch_reserved[32];
/** Offset 0x04C6**/ uint8_t s0i3_enable;
/** Offset 0x04C7**/ uint32_t telemetry_vddcrvddfull_scale_current;
/** Offset 0x04CB**/ uint32_t telemetry_vddcrvddoffset;
/** Offset 0x04CF**/ uint32_t telemetry_vddcrsocfull_scale_current;
/** Offset 0x04D3**/ uint32_t telemetry_vddcrsocOffset;
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
/** Offset 0x04D8**/ uint32_t usb_phy_ptr;
/** Offset 0x04DC**/ uint64_t xgbe_port0_mac;
/** Offset 0x04E4**/ uint64_t xgbe_port1_mac;
/** offset 0x04EC**/ uint8_t xgbe_port0_config_en;
/** offset 0x04ED**/ uint8_t xgbe_port1_config_en;
/** offset 0x04EE**/ uint32_t xgbe_port0_table;
/** offset 0x04F2**/ uint32_t xgbe_port1_table;
/** offset 0x04F6**/ uint8_t nvme_rst_gpio;
/** Offset 0x04F7**/ uint8_t UnusedUpdSpace2[265];
/** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
**/
typedef struct __packed {
/** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040**/ FSP_M_CONFIG FspmConfig;
} FSPM_UPD;
#define IMAGE_REVISION_MAJOR_VERSION 0x01
#define IMAGE_REVISION_MINOR_VERSION 0x00
#define IMAGE_REVISION_REVISION 0x05
#define IMAGE_REVISION_BUILD_NUMBER 0x00
#endif

26
src/vendorcode/amd/fsp/renoir/FspsUpd.h Normal file
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@ -0,0 +1,26 @@
/** @file
*
* This file is automatically generated.
*
*/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#include <FspUpd.h>
typedef struct __packed {
/** Offset 0x0020**/ uint32_t vbios_buffer;
/** Offset 0x0024**/ uint64_t gop_reserved;
/** Offset 0x002C**/ uint32_t reserved1;
/** Offset 0x0030**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct __packed {
/** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
} FSPS_UPD;
#endif

17
src/vendorcode/amd/fsp/renoir/ccx_cppc_data.h Normal file
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@ -0,0 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef CEZANNE_FSP_CCX_CPPC_DATA_H
#define CEZANNE_FSP_CCX_CPPC_DATA_H
#include <types.h>
#define FSP_CCX_CPPC_DATA_VERSION 1
struct fsp_ccx_cppc_data {
uint8_t version;
uint8_t unused[3];
uint32_t ccx_cppc_min_speed;
uint32_t ccx_cppc_nom_speed;
} __packed;
#endif /* CEZANNE_FSP_CCX_CPPC_DATA_H */

58
src/vendorcode/amd/fsp/renoir/fsp_h_c99.h Normal file
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@ -0,0 +1,58 @@
/** @file
*
* C99 common FSP definitions from
* Intel Firmware Support Package External Architecture Specification v2.0
*
* These definitions come in a format that is usable outside an EFI environment.
**/
#ifndef FSP_H_C99_H
#define FSP_H_C99_H
#include <stdint.h>
enum {
FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001,
FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002,
FSP_STATUS_RESET_REQUIRED_3 = 0x40000003,
FSP_STATUS_RESET_REQUIRED_4 = 0x40000004,
FSP_STATUS_RESET_REQUIRED_5 = 0x40000005,
FSP_STATUS_RESET_REQUIRED_6 = 0x40000006,
FSP_STATUS_RESET_REQUIRED_7 = 0x40000007,
FSP_STATUS_RESET_REQUIRED_8 = 0x40000008,
};
typedef enum {
EnumInitPhaseAfterPciEnumeration = 0x20,
EnumInitPhaseReadyToBoot = 0x40,
EnumInitPhaseEndOfFirmware = 0xF0
} FSP_INIT_PHASE;
typedef struct __packed {
uint64_t Signature;
uint8_t Revision;
uint8_t Reserved[23];
} FSP_UPD_HEADER;
_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
#if CONFIG(PLATFORM_USES_FSP2_X86_32)
typedef struct __packed {
uint8_t Revision;
uint8_t Reserved[3];
/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
uint32_t NvsBufferPtr;
/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
uint32_t StackBase;
uint32_t StackSize;
uint32_t BootLoaderTolumSize;
uint32_t BootMode;
uint8_t Reserved1[8];
} FSPM_ARCH_UPD;
_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
#else
#error You need to implement this struct for x86_64 FSP
#endif
#endif /* FSP_H_C99_H */

333
src/vendorcode/amd/fsp/renoir/platform_descriptors.h Normal file
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@ -0,0 +1,333 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* These definitions are used to describe PCIe bifurcation and display physical
* connector types connected to the SOC.
*/
#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H
#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H
#define NUM_DXIO_PHY_PARAMS 6
#define NUM_DXIO_PORT_PARAMS 6
/* Engine descriptor type */
enum dxio_engine_type {
UNUSED_ENGINE = 0x00, // Unused descriptor
PCIE_ENGINE = 0x01, // PCIe port
USB_ENGINE = 0x02, // USB port
SATA_ENGINE = 0x03, // SATA
DP_ENGINE = 0x08, // Digital Display
ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe)
MAX_ENGINE // Max engine type for boundary check.
};
/* PCIe link capability/speed */
enum dxio_link_speed_cap {
GEN_MAX = 0, // Maximum supported
GEN1,
GEN2,
GEN3,
GEN_INVALID // Max Gen for boundary check
};
/* Upstream Auto Speed Change Allowed */
enum dxio_upstream_auto_speed_change {
SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3
SPDC_DISABLED,
SPDC_ENABLED,
SPDC_INVALID
};
/* SATA ChannelType initialization */
enum dxio_sata_channel_type {
SATA_CHANNEL_OTHER = 0, // Default Channel Type
SATA_CHANNEL_SHORT, // Short Trace Channel Type
SATA_CHANNEL_LONG // Long Trace Channel Type
};
/* CLKREQ for PCIe type descriptors */
enum cpm_clk_req {
CLK_DISABLE = 0x00,
CLK_REQ0,
CLK_REQ1,
CLK_REQ2,
CLK_REQ3,
CLK_REQ4_GFX,
CLK_REQ5,
CLK_REQ6,
CLK_ENABLE = 0xff,
};
/* PCIe link ASPM initialization */
enum dxio_aspm_type {
ASPM_DISABLED = 0, // Disabled
ASPM_L0s, // PCIe L0s link state
ASPM_L1, // PCIe L1 link state
ASPM_L0sL1, // PCIe L0s & L1 link state
ASPM_MAX // Not valid value, used to verify input
};
/* PCIe link hotplug */
enum dxio_link_hotplug_type {
HOTPLUG_DISABLED = 0,
HOTPLUG_BASIC,
HOTPLUG_SERVER,
HOTPLUG_ENHANCED,
HOTPLUG_INBOARD,
HOTPLUG_SERVER_SSD,
};
enum dxio_port_param_type {
PP_DEVICE = 1,
PP_FUNCTION,
PP_PORT_PRESENT,
PP_LINK_SPEED_CAP,
PP_LINK_ASPM,
PP_HOTPLUG_TYPE,
PP_CLKREQ,
PP_ASPM_L1_1,
PP_ASPM_L1_2,
PP_COMPLIANCE,
PP_SAFE_MODE,
PP_CHIPSET_LINK,
PP_CLOCK_PM,
PP_CHANNELTYPE,
PP_TURN_OFF_UNUSED_LANES,
PP_APIC_GROUPMAP,
PP_APIC_SWIZZLE,
PP_APIC_BRIDGEINT,
PP_MASTER_PLL,
PP_SLOT_NUM,
PP_PHY_PARAM,
PP_ESM,
PP_CCIX,
PP_GEN3_DS_TX_PRESET,
PP_GEN3_DS_RX_PRESET_HINT,
PP_GEN3_US_TX_PRESET,
PP_GEN3_US_RX_PRESET_HINT,
PP_GEN4_DS_TX_PRESET,
PP_GEN4_US_TX_PRESET,
PP_GEN3_FIXED_PRESET,
PP_GEN4_FIXED_PRESET,
PP_PSPP_DC,
PP_PSPP_AC,
PP_GEN2_DEEMPHASIS,
PP_INVERT_POLARITY,
PP_TARGET_LINK_SPEED,
PP_GEN4_DLF_CAP_DISABLE,
PP_GEN4_DLF_EXCHG_DISABLE
};
/* DDI Aux channel */
enum ddi_aux_type {
DDI_AUX1 = 0,
DDI_AUX2,
DDI_AUX3,
DDI_AUX4,
DDI_AUX5,
DDI_AUX6,
DDI_AUX_MAX // Not valid value, used to verify input
};
/* DDI Hdp Index */
enum ddi_hdp_type {
DDI_HDP1 = 0,
DDI_HDP2,
DDI_HDP3,
DDI_HDP4,
DDI_HDP5,
DDI_HDP6,
DDI_HDP_MAX // Not valid value, used to verify input
};
/* DDI display connector type */
enum ddi_connector_type {
DDI_DP = 0, // DP
DDI_EDP, // eDP
DDI_SINGLE_LINK_DVI, // Single Link DVI-D
DDI_DUAL_LINK_DVI, // Dual Link DVI-D
DDI_HDMI, // HDMI
DDI_DP_TO_VGA, // DP-to-VGA
DDI_DP_TO_LVDS, // DP-to-LVDS
DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA
DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I
DDI_CRT, // CRT (VGA)
DDI_LVDS, // LVDS
DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init
DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init
DDI_AUTO_DETECT, // VBIOS auto detect connector type
DDI_UNUSED_TYPE, // UnusedType
DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input
};
/* DDI Descriptor: used for configuring display outputs */
typedef struct __packed {
uint8_t connector_type; // see ddi_connector_type
uint8_t aux_index; // see ddi_aux_type
uint8_t hdp_index; // see ddi_hdp_type
uint8_t reserved;
} fsp_ddi_descriptor;
/*
* Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines,
* configure bifurcation and other settings. Beware that the lane numbers in
* here are the logical and not the physical lane numbers!
*
* Cezanne DXIO logical lane to physical PCIe lane mapping:
*
* logical | FT6 | AM4
* --------|------------|----------------------
* [00:03] | GPP[00:03] | GPP[00:03]
* [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03]
* [08:11] | GPP[08:11] | GFX[15:12]
* [12:15] | n/a | GFX[11:08]
* [16:23] | GFX[00:07] | GFX[07:0]
*
* Different ports mustn't overlap or be assigned to the same lane(s). Within
* ports with the same width the one with a higher start logical lane number
* needs to be assigned to a higher PCIe root port number; ports of the same
* size don't have to be assigned to consecutive PCIe root ports though.
*
* Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6
* platform additionally supports mapping lanes 8 and 9 to a SATA controller.
* On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet
* controllers.
*/
typedef struct __packed {
uint8_t engine_type; // See dxio_engine_type
uint8_t start_logical_lane; // Start lane of the pci device
uint8_t end_logical_lane; // End lane of the pci device
uint8_t gpio_group_id; // GPIO number used as reset
uint32_t port_present :1; // Should be TRUE if train link
uint32_t reserved_3 :7;
uint32_t device_number :5; // Desired root port device number
uint32_t function_number :3; // Desired root port function number
uint32_t link_speed_capability :2; // See dxio_link_speed_cap
uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change
uint32_t eq_preset :4; // Gen3 equalization preset
uint32_t link_aspm :2; // See dxio_aspm_type
uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1
uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2
uint32_t clk_req :4; // See cpm_clk_req
uint8_t link_hotplug; // See dxio_link_hotplug_type
uint8_t slot_power_limit; // Currently unused by FSP
uint32_t slot_power_limit_scale :2; // Currently unused by FSP
uint32_t reserved_4 :6;
uint32_t link_compliance_mode :1; // Currently unused by FSP
uint32_t link_safe_mode :1; // Currently unused by FSP
uint32_t sb_link :1; // Currently unused by FSP
uint32_t clk_pm_support :1; // Currently unused by FSP
uint32_t channel_type :3; // See dxio_sata_channel_type
uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present
uint8_t reserved[4];
uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2];
uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type
} fsp_dxio_descriptor;
typedef enum {
XGBE_PORT_DISABLE,
XGBE_PORT_ENABLE,
} xgbe_port_enable;
typedef enum {
XGBE_PHY_MODE_RJ45,
XGBE_PHY_MODE_SFP_PLUS,
XGBE_PHY_MODE_BACKPLANE
} xgbe_port_phy_modes;
typedef enum {
XGBE_RESERVED,
XGBE_10G_1G_BACKPLANE,
XGBE_2_5G_BACKPLANE,
XGBE_SOLDERED_DOWN_1000BASE_T,
XGBE_SOLDERED_DOWN_1000BASE_X,
XGBE_SOLDERED_DOWN_NBASE_T,
XGBE_SOLDERED_DOWN_10GBASE_T,
XGBE_SOLDERED_DOWN_10GBASE_R,
XGBE_SFP_PLUS_CONNECTOR,
BACKPLANE_AUTONEG_OFF
} xgbe_port_platform_config;
typedef enum {
XGBE_PORT_SPEED_10M = 0x1,
XGBE_PORT_SPEED_100M = 0x2,
XGBE_PORT_SPEED_1G = 0x4,
XGBE_PORT_SPEED_10_100_1000M = 0x7,
} xgbe_port_speed_config;
typedef enum {
XGBE_PORT_NOT_USED = 0x0,
XGBE_SFP_PLUS_CONNECTION = 0x1,
XGBE_CONNECTION_MDIO_PHY = 0x2,
XGBE_BACKPLANE_CONNECTION = 0x4,
} xgbe_port_connection_type;
struct __packed xgbe_port_table {
uint8_t xgbe_port_config; ///< XGbE controller Port Config Enable/disable
uint8_t xgbe_port_platform_config; ///< Platform Config
/// @li <b>0000</b> - Reserved
/// @li <b>0001</b> - 10G/1G Backplane
/// @li <b>0010</b> - 2.5G Backplane
/// @li <b>0011</b> - 1000Base-T
/// @li <b>0100</b> - 1000Base-X
/// @li <b>0101</b> - NBase-T
/// @li <b>0110</b> - 10GBase-T
/// @li <b>0111</b> - 10GBase-X
/// @li <b>1000</b> - SFP+
uint8_t xgbe_port_supported_speed; ///< Indicated Ethernet speeds supported on platform
/// @li <b>x111</b> - 10/100/1000M
/// @li <b>x1xx</b> - 1G
/// @li <b>xx1x</b> - 100M
/// @li <b>xxx1</b> - 10M
uint8_t xgbe_port_connected_type; ///< PHY connected type
/// @li <b>000</b> - Port not used
/// @li <b>001</b> - SFP+
/// @li <b>010</b> - MDIO
/// @li <b>100</b> - Backplane connection
uint8_t xgbe_port_mdio_id; ///< MDIO ID of the PHY associated with this port
uint8_t xgbe_port_mdio_reset_type; ///< MDIO PHY reset type
/// @li <b>00</b> - None
/// @li <b>01</b> - I2C GPIO
/// @li <b>10</b> - Integrated GPIO
/// @li <b>11</b> - Reserved
uint8_t xgbe_port_reset_gpio_num; ///< GPIO used to control the reset
uint8_t xgbe_port_mdio_reset_i2c_address; ///< I2C address of PCA9535 MDIO reset GPIO
uint8_t xgbe_port_sfp_i2c_address; ///< I2C address of PCA9535 for SFP
uint8_t xgbe_port_sfp_tx_fault_gpio; ///< GPIO number for SFP+ TX_FAULT
uint8_t xgbe_port_sfp_rs_gpio; ///< GPIO number for SFP+ RS
uint8_t xgbe_port_sfp_mod_abs_gpio; ///< GPIO number for SFP+ Mod_ABS
uint8_t xgbe_port_sfp_rx_los_gpio; ///< GPIO number for SFP+ Rx_LOS
uint8_t xgbe_port_sfp_gpio_mask; ///< GPIO Mask for SFP+
/// @li <b>1xxx</b> - Rx_LOS not supported
/// @li <b>x1xx</b> - Mod_ABS not supported
/// @li <b>xx1x</b> - RS not supported
/// @li <b>xxx1</b> - TX_FAULT not supported
uint8_t xgbe_port_sfp_twi_address; ///< Address of PCA9545 I2C multiplexor
uint8_t xgbe_port_sfp_twi_bus; ///< Downstream channel of PCA9545
uint8_t xgba_port_redriver_present; ///< Redriver Present or not
uint8_t reserve0[3]; ///< Reserved
uint8_t xgba_port_redriver_model; ///< Redriver Model
/// @li <b>00</b> - InPhi 4223
/// @li <b>01</b> - InPhi 4227
uint8_t xgba_port_redriver_interface; ///< Redriver Interface
/// @li <b>00</b> - MDIO
/// @li <b>01</b> - I2C
uint8_t xgba_port_redriver_address; ///< Redriver Address
uint8_t xgba_port_redriver_lane; ///< Redriver Lane
uint8_t xgba_port_pad_gpio; ///< Portx_GPIO Pad selection
/// @li <b>001</b> - MDIO0 pin
/// @li <b>010</b> - MDIO1 pin
/// @li <b>100</b> - SFP pin
uint8_t xgba_port_pad_mdio; ///< Portx_Mdio Pad selection
/// @li <b>001</b> - MDIO0 pin
/// @li <b>010</b> - MDIO1 pin
/// @li <b>100</b> - SFP pin
uint8_t xgba_port_pad_i2c; ///< Portx_I2C Pad selection
/// @li <b>001</b> - MDIO0 pin
/// @li <b>010</b> - MDIO1 pin
/// @li <b>100</b> - SFP pin
uint8_t reserve1; ///< Reserved
};
#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */

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src/vendorcode/amd/fsp/renoir/soc_dmi_info.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* These definitions are used to describe memory modules physical layout
*/
#ifndef SOC_DMI_INFO_H
#define SOC_DMI_INFO_H
#define AGESA_STRUCT_SOCKET_COUNT 2 ///< Number of sockets in AGESA FSP DMI T17 table
#define AGESA_STRUCT_CHANNELS_PER_SOCKET 8 ///< Channels per socket in AGESA FSP DMI T17 table
#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table
#define AGESA_STRUCT_PART_NUMBER_SIZE 21 //TODO check
#define SMBIOS_3_2_3_3_SUPPORT 1
#endif /* SOC_DMI_INFO_H */