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soc/intel/pantherlake: Fix IA domain TDC value for PTL_TDC_2 SKU

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Align the IA domain Thermal Design Current (TDC) value for PTL_TDC_2
with Document #813289 power map revision 2.1. The previous value 23A did
not match the updated specification, which now requires 28A. This change
ensures that the firmware correctly reflects the hardware power limits
for this SKU, preventing potential power delivery issues and improving
system stability.

Change-Id: I16bb510b8ec2ad1ffdeba20bfe26d0cbad209088
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2025-11-06 12:52:22 -08:00 • committed by Matt DeVillier
commit b0ee0c4620
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/pantherlake/chipset_ptl.cb
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@ -13,7 +13,7 @@ chip soc/intel/pantherlake
[VR_DOMAIN_GT] = 15 * 8
}"
register "thermal_design_current[PTL_TDC_2]" = "{
[VR_DOMAIN_IA] = 23 * 8,
[VR_DOMAIN_IA] = 28 * 8,
[VR_DOMAIN_GT] = 23 * 8
}"
register "icc_max[PTL_SKU_1]" = "{