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mb/siemens/mc_ehl6: Adjust I2C setup

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Adapt I2C controller configuration for mc_ehl6 board. This involves
changes to the coreboot I2C setup. To prevent higher I2C speeds from
being used by the OS, dummy devices are installed on the I2C bus.

TEST=Check if drivers for the I2C devices started correctly during
coreboot execution and verify that all I2C devices are detected in the
OS.

Change-Id: I6de578f969456a15807a1380209ea18e01f522bd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Uwe Poeche 2025-07-09 11:49:11 +02:00 • committed by Matt DeVillier
commit 864e3ca661
1 changed files with 35 additions and 29 deletions
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68
src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
View file

@ -78,16 +78,23 @@ chip soc/intel/elkhartlake
# LPSS Serial IO (I2C/UART/GSPI) related UPDs
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoPci,
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}"
register "SerialIoI2cPadsTermination" = "{
[PchSerialIoIndexI2C1] = 1,
[PchSerialIoIndexI2C2] = 1,
[PchSerialIoIndexI2C4] = 1,
[PchSerialIoIndexI2C6] = 1,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
@ -109,26 +116,6 @@ chip soc/intel/elkhartlake
register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
register "common_soc_config" = "{
.i2c[1] = {
.speed = I2C_SPEED_STANDARD,
.speed_config[0] = {
.speed = I2C_SPEED_STANDARD,
.scl_hcnt = 0x1e1,
.scl_lcnt = 0x1f4,
.sda_hold = 0x64
},
},
.i2c[2] = {
.speed = I2C_SPEED_STANDARD,
.speed_config[0] = {
.speed = I2C_SPEED_STANDARD,
.scl_hcnt = 0x1df,
.scl_lcnt = 0x1f4,
.sda_hold = 0x64
},
},
}"
# FIVR related settings
register "fivr" = "{
@ -146,9 +133,17 @@ chip soc/intel/elkhartlake
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 10.0 on # I2C6
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
chip drivers/i2c/generic
register "hid" = ""PRP0001""
register "speed" = "I2C_SPEED_STANDARD"
device i2c 0x7f on end
end
end
device pci 14.0 on end # USB3.1 xHCI
device pci 15.0 on end # I2C0
device pci 15.1 on # I2C1
# Enable external RTC chip
chip drivers/i2c/rv3028c7
@ -162,21 +157,32 @@ chip soc/intel/elkhartlake
register "cap_charge" = "CHARGE_OFF"
device i2c 0x52 on end # RTC RV3028-C7
end
end
device pci 15.2 on # I2C2
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
chip drivers/i2c/generic
register "hid" = ""PRP0001""
register "speed" = "I2C_SPEED_STANDARD"
device i2c 0x7f on end
end
end
device pci 15.2 on # I2C2
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
chip drivers/i2c/generic
register "hid" = ""PRP0001""
register "speed" = "I2C_SPEED_STANDARD"
device i2c 0x7f on end
end
end
device pci 15.3 on end # I2C3
device pci 16.0 hidden end # Management Engine Interface 1
device pci 19.0 on end # I2C4
device pci 19.1 on end # I2C5
device pci 19.0 on # I2C4
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
chip drivers/i2c/generic
register "hid" = ""PRP0001""
register "speed" = "I2C_SPEED_STANDARD"
device i2c 0x7f on end
end
end
device pci 19.2 on end # UART2
device pci 1a.0 on end # eMMC